• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.134-135
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• 2007

Growth of cubic SiC has been carried out on oxided Si substrate using atmospheric pressure chemical vapor deposition (APCVD). Hexamethyldisilane (HMDS) was used as the single precursor and nonflammable mixture of Ar and $H_2$ was used as carrier gas. Epitaxial growth had performed depositions under the various $H_2$ conditions which were adjusted from 0 to 100 seem. The effects of $H_2$ was characterized by surface roughness, thickness uniformity, films quality and elastic modulus. Thickness uniformity and films quality were performed by SEM. Surface roughness and elastic modulus were investigated by AFM and Nano-indentor, respectively. According to the $H_2$ flow rate, Poly 3C-SiC thin film quality was improved not only physical but also mechanical properties.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.396-401
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• 1999

In this study, $Ar^+$ ion laser etching process of single/poly-crystalline Si with $CCl_2F_2$ gas is investigated for MEMS applications. In general, laser direct etching process is useful in microelectronic process, fabrication of micro sensors and actuators, rapid prototyping, and complementary processing because of the advantages of 3D micromachining, local etching/deposition process, and maskless process with high resolution. In this study, a pyrolytic method, in which $CCl_2F_2$ gasetches molten Si by the focused laser, was used. In order to analyze the temperature profile of Si by the focused laser, the 3D heat conduction equation was analytically solved. In order to investigate the process parameters dependence of etching characteristics, laser power, $CCl_2F_2$ gas pressure, and scanning speed were varied and the experimental results were observed by SEM. The aspect ratio was measured in multiple scanning and the simple 3D structure was fabricated. In addition, the etching characteristics of $6\mum$ thick poly-crystalline Si on the insulator was investigated to obtain flat bottom and vertical side wall for MEMS applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.322-325
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• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 한국주조공학회지
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• 제25권3호
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• pp.115-122
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• 2005

In the present study, an EMC (Electromagnetic Casting) process, using a segmented Cu cold crucible under a high frequency alternating magnetic field of 20 kHz, was practiced for the fabrication of poly-crystalline Si ingot of 50 mm diameter. The effects of Joule heating and electromagnetic pressure in molten Si were systematically investigated with various processing parameters such as electric current and crucible configuration. A preliminary experimental work was initiated with the pure Al system for the establishment of a stabilized non-contact working condition, and further adapted to the semiconductor-off-grade Si system. A commercialized software such as Opera-3D was utilized in order to simulate electromagnetic pressure and Joule heating. In order to evaluate the meniscus shape of the molten melts, shape parameter was used throughout the research. A segmented graphite crucible, which was attached at the upper part of the cold crucible, was introduced to enhance significantly the heating efficiency of Si melt keeping non-contact condition during continuous melting and casting processes.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1019-1022
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• 2004

High performance p-ch poly-Si TFTs with excellent stability were developed. By using a frequency doubled DPSS CW laser, the a-Si on glass could be crystallized into one dimensional single crystalline silicon named as a sequential lateral crystallization (SLC) region. We fabricated p-ch TFTs on SLC region and the typical characteristic values of the TFTs were $u_{fe}$ = 180 $cm^2$/Vs, $V_{th}$ = -3 V, S.S. = 0.5 V/dec, and $I_{off}$ = 1 pA/um@ $V_d$ = -10V. It is found that the TFTs are very stable after bias stresses such as negative and positive gate biases, hot carrier bias and high current bias. These results indicate that the poly-Si in SLC region is suitable for system on glass (SOG) application.

• Applied Science and Convergence Technology
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• 제24권6호
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• pp.268-272
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• 2015

We report the systematic study to reduce extrinsic doping in graphene grown by chemical vapor deposition (CVD). To investigate the effect of crystallinity of graphene on the extent of the extrinsic doping, graphene samples with different levels of crystal quality: poly-crystalline and single-crystalline graphene (PCG and SCG), are employed. The graphene suspended in air is almost undoped regardless of its crystallinity, whereas graphene placed on an $SiO_2/Si$ substrate is spontaneously p-doped. The extent of p-doping from the $SiO_2$ substrate in SCG is slightly lower than that in PCG, implying that the defects in graphene play roles in charge transfer. However, after annealing treatment, both PCG and SCG are heavily p-doped due to increased interaction with the underlying substrate. Extrinsic doping dramatically decreases after annealing treatment when PCG and SCG are placed on the top of hexagonal boron nitride (h-BN) substrate, confirming that h-BN is the ideal substrate for reducing extrinsic doping in CVD graphene.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.275-275
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• 2008

This paper describe the fabrication of a Pd/polycrystalline 3C-SiC schottky diode and its characteristics, in which the polycrystalline 3C-SiC layer and Pd Schottky contact were deposited by using APCVD and sputter, respectively. Crystalline quality, uniformity, and preferred orientations of the Pd thin film were evaluated by SEM and XRD, respectively. Pd/poly 3C-SiC Schottky diodes were fabricated and characterized by I-V and C-V measurements. Its electric current density Js and barrier height voltage were measured as $2\times10^{-3}$ A/$cm^2$ and 0.58 eV, respectively. These devices were operated until about $400^{\circ}C$. Therefore, from these results, Pd/poly 3C-SiC Schottky devices have very high potential for high temperature chemical sensor applications.

• 한국주조공학회지
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• 제20권3호
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• pp.188-196
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• 2000

A vacuum casting was proposed as a new fabrication method of Si wafer for solar cell substrate. It was tried to fabricate a Si plate with good properties and to reduce the production cost by direct vacuum casting. By $5{\sim}10$ cmHg of pressure difference Si plate with $50{\times}46{\times}1.5\;mm^3$ was fabricated. For the preventing of the reaction between graphite mold and Si melt, BN powder coating or BN insert were used. The Si wafer was poly crystalline with 100 ${\mu}m{\sim}1$ mm order of grain size. And there were some twins and dislocations in the grains.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.194-194
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• 2009

3C-SiC thin films are widely used in extreme environments, radio frequency (RF) environments, and bio-materials for micro/nano electronic mechanical systems (M/NEMS). The mechanical properties of 3C-SiC thin films need to be considered when designing M/NEMS, so Young's Modulus and the hardness need to be accurately measured. Young's Modulus and the hardness are influenced by N-doping. In this paper, we show that the mechanical properties of poly (polycrystalline) 3C-SiC thin films are influenced by the N-doping concentration. Furthermore, we measure the mechanical properties of 3C-SiC thin films for N-doping concentrations of 1%, 3%, and 5%, by using nanoindentation. For films deposited using a 1% N-doping concentration, Young's Modulus and the hardness were measured as 270 GPa and 30 GPa, respectively. When the surface roughness of the thin films was investigated by using atomic force microscopy (AFM), the roughness of the 5% N-doped 3C-SiC thin film was the lowest of all the films, at 15 nm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.