• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.264.1-264.1
• /
• 2014

현재 디스플레이에서 가장 널리 이용되는 ELA poly-Si TFT의 표면 거칠기 등으로 인한 대면적 문제를 해결하고자 연구 중인 MIC 방식의 ULG poly-Si TFT를 이용한 게이트-바이어스 스트레스에 따른 전기적 특성을 비교하고자 한다. Positive gate bias의 경우 20V의 게이트 전압과 -0.1V의 드레인 전압에서 10,000초 동안 비교 측정하였으며, 이때 ${\Delta}VTH$는 ELA poly-Si TFT가 143.6 mV, ULG poly-Si TFT가 28.8 mV였다. 또한 negative gate bias의 경우 -20 V의 게이트 전압과 -0.1 V의 드레인 전압에서 10,000초 동안 비교 측정하였으며, 이때 ${\Delta}VTH$는 ELA poly-Si TFT가 154.4 mV, ULG poly-Si TFT가 70.8 mV였다. 이는 게이트 절연막과 채널층 사이의 계면에서 높은 표면 거칠기로 인한 전계의 차이에 의해 더 많은 전하의 트랩에 기인한 것이다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.287.1-287.1
• /
• 2014

본 연구에서는 현재 디스플레이에서 가장 널리 이용되는 저온 polycrystalline silicon (poly-Si)의 결정화 방법에 따른 thin-film transistor (TFT)의 전기적 특성을 분석하였다. 분석에 이용된 결정화 방식은 Excimer Laser Annealing (ELA)와 Metal Induced Crystallization (MIC)이다. ELA와 MIC TFTs의 전기적 특성 측정을 통한 분석결과 ELA와 MIC poly-Si TFTs의 전기적 특성 [field-effect mobility (${\mu}_{FE}$), on/off current ratio ($I_{ON}/I_{OFF}$), sub-threshold swing (SS)]은 큰 차이는 없지만, ELA를 이용한 poly-Si TFT의 전기적 특성이 조금 우수하다. 하지만, MIC poly-Si TFT의 경우 threshold voltage ($V_{TH}$)가 0V에 보다 가까울 뿐만 아니라, 전기적 스트레스를 통한 신뢰성 확인 시 ELA poly-Si TFT보다 조금 더 안정적이다. 이는 ELA의 경우 좁은 면에 선형 레이저 빔으로 조사하면서 생기는 hill-lock의 영향으로 표면이 거칠고 균일하지 못하여 바이어스 인가시 생기는 문제이다. 또한 MIC는 금속 촉매를 이용해 결정립 경계를 확장하고 결정 크기를 키워 대면적화에 유리하다. Thermal Stress에서는 (from 293K to 373K) TFT에 점차 높은 온도를 가하자 MIC poly-Si TFT의 경우 off 상태에서 누설 전류 값이 증가하며 열에 민감한 반응을 보이는 것을 확인하였다.

• Electrical & Electronic Materials
• /
• v.9 no.1
• /
• pp.30-37
• /
• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.05a
• /
• pp.90-93
• /
• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.06a
• /
• pp.125-126
• /
• 2007

Polycrystalline silicon thin-film-transistors (Poly-Si TFT's) with a amorphous-$Si_xGe_y$ seed layer have been fabricated to improve the performance of TFT. The dependence of crystal structure and electrical characteristics on the the Ge fractions in $Si_xGe_y$ seed layer were investigated. As a result, the increase of grain size and enhancement of electrical characteristics were obtained from the poly-Si TFT's with amorphous-SixGey seed layer.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.2002-2007
• /
• 1999

In this paper, the n-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) on glass were investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. It is done to decide to be applied on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 2, 10, 25$\mu\textrm{m}$ of channel length, the field effect mobilities are 111, 126 and 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus, the poly-Si TFT’s used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate display panel and peripheral circuit on a large glass substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.9
• /
• pp.683-686
• /
• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.141-144
• /
• 1998

The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.12
• /
• pp.1065-1070
• /
• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.81-84
• /
• 2004

Required characteristics of poly-Si TFT's are investigated for the implementation of analog circuits to be integrated on System-on-Glass (SoG). Matching requirements on resistor values, threshold voltage and mobility of poly-Si TFT's are derived as a function of the resolution of display system. Effective mobility of poly-Si TFT's required for the realization of source driver is analyzed for various panel sizes.