• 대한전자공학회논문지
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• 제26권4호
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• pp.88-97
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• 1989

본 논문에서 제안하는 switch-box 배선기는 greedy poly-jog 배선기와 via 최소화기로 나누어진다. Greedy poly-jog 배선기는 Luk의 greedy swich-box 배선 알고리듬을 기본으로 하며, 수평track에 metal을 수직track에 poly-silicon을 배선하는 제한을 완화하여 필요한 경우에는 수평 track에 poly-silicon을 배선함으로써 배선영역의 수평track을 증가시키지 않고 배선할 수 있다. Via 최소화기는 배선된 wire의 각 corner를 펴거나 wire 선분을 평행이동하거나 metal을 poly-silicon 및 poly-silicon을 metal로 바꿈으로써 via와 배선길이를 줄이는 과정을 수행한다. 본 배선기는 column 방향으로 배선영역을 scan함으로써 배선을 완료하며, 시간복잡도는 O(M(N+ Nnet)) 이다. 여기서, M, N, Nnet은 각각 배선 column의 수, 배선 row의 수, net의 수이다.

• 센서학회지
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• 제5권1호
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• pp.71-77
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• 1996

마이크로머시닝의 구조재료인 다결정 Si이 희생산화막의 영향을 받음을 고려하여 다결정 Si을 열산화시킨 다결정-산화막을 새로운 희생산화막의 재료로서 제안하고 평가하였다. 다결정-산화막상에 성장시킨 다결정 Si은 통상의 희생산화막상에 성장시키는 경우보다 grain size가 증가하였고, XRD결과를 통해 (111) texture의 증가와, 부가적인 (220) texture가 형성됨을 관찰하였다. 또한, 다결정-산화막상에 성장시킨 다결정 Si의 경우, 그 응력이 작고 균일한 분포를 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.677-680
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• 1999

Rapid developing automation technology enhances the need of sensors. Among many materials, silicon has the advantages of electrical and mechanical property, Single-crystalline silicon has different piezoresistivity on 야fferent directions and a current leakage at elevated temperature, but poly-crystalline silicon has the possibility of controling resistivity using dopping ions, and operation at high temperature, which is grown on insulating layers. Each wafer has slightly different thicknesses that make difficult to obtain the precisely same thickness of a diaphragm. This paper deals with the fabrication process to make poly-crystalline silicon based pressure sensors which includes diaphragm thickness and wet-etching techniques for each layer. Diaphragms of the same thickness can be fabricated consisting of deposited layers by silicon bulk etching. HF etches silicon nitride, HNO$_3$+HF does poly -crystalline silicon at room temperature very fast. Whereas ethylenediamice based etchant is used to etch silicon at 11$0^{\circ}C$ slowly.

• 대한전자공학회논문지
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• 제24권2호
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• pp.248-253
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• 1987

Boron diffusion into silicon through poly\ulcorneri-SiO2 was carried out for the diffusion with low concentration using CVD-BN. The result of direct boron diffusion from BN into silicon and that of boron diffusion through SiO2 from BN into silicon was compared with the result of boron diffusion through poly-Si-SiO2 from BN into silicon. In the case of boron diffusion through poly Si-SiO2, the low concentration diffusion was obtained, that is the boron surface concentration in silicon Cs=10**16 Cm**-3, and the glassy compounds were not seen.

• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.199-199
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• 2008

이 실험은 NVM의 Oxide, Nitride, Oxide nitride층별 blocking, trapping and tunneling 속성에 대해서 밝히고자 한다. gate 전극은 값싸고 전도도가 좋은 알루미늄을 사용한다. 유리기판위에 Silicon nitride층을 20nm로 코팅하고 Silicon dioxide층을 10nm로 코팅한다. 그리고 amorphous Silicon material이 증착된다. Poly Silicon은 Solid Phase Crystallization 방법을 사용하였다. 마지막 공정으로 p-doping은 ion shower에 의한 방법으로 drain과 source 전극을 생성하였다. gate가 biasing 될 때, p-channel은 source와 drain 사이에서 형성된다. Oxide Nitride Oxide nitride (ONO) 층은 각각 12.5nm/20nm/2.3nm의 두께로 만들었다. 전하는 Program process 중에 poly Silicon층에서 Silicon Oxide nitride tunneling층을 통하여 움직이게 된다. 그리고 전하들은 Silicon Nitride층에 머무르게 된다. 그 전하들은 erasing process 중에 trapping 층에서 poly Silicon 층으로 되돌아 간다. Silicon Oxide blocking층은 trapping층으로 전하가 나가는 것을 피하기 위하여 더해진다. 이 논문에서 Programming process와 erasing process의 Id-Vg 특성곡선을 설명한다. Programming process에 positive voltage를 또는 erasing process에 negative voltage를 적용할 때, Id-Vg 특성 곡선은 왼쪽 또는 오른쪽으로 이동한다. 이 실험이 보여준 결과값에 의해서 10년 이상의 저장능력이 있는 메모리를 만들 수 있다. 그러므로, NVM의 중요한 두 가지 성질은 유지성과 내구성이다.

• 한국전기전자재료학회논문지
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• 제24권7호
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 반도체디스플레이기술학회지
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• 제4권1호
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• pp.23-27
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• 2005

This paper presents a simulation methodology for the poly-silicon oriented TCAD(technology-CAD) system. A computer simulation environment for the poly-silicon processing has been set up with the proper adoption of the two-stream model for ion-doping, diffusion, and defects inside of grain and on the grain boundary. After the simulator calibration, simulation results for the poly-silicon diffusion hat shown a good agreement with the SIMS data.

• 한국산학기술학회논문지
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• 제5권3호
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• pp.210-217
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• 2004

본 연구는 기존 반도체 단위공정의 실리콘 중심 CAD 환경을 다결정실리콘 중심의 환경으로 전환하는 방법론에 대해 제안하였다. 다결정실리콘 공정에서의 확산과 이온도핑에 의한 불순물 이동에 관련하여 결정립내부와 결정립계상에서의 확산을 동시에 고려하는 이중흐름(two-stream)모델을 채택하고, 이와 관련된 파라미터들의 민감도 분석을 통하여 다결정실리콘 컴퓨터 시뮬레이션 환경을 재구성하였다. 시뮬레이터의 캘리브레이션 과정을 거친 결과 다결정실리콘에 대한 SIMS 데이터와 전반적으로 잘 일치하였다.