• 천문학회보
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• 제39권2호
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• pp.103-103
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• 2014

Manufacturing of lens and mirror using Diamond Turning Machine (DTM) offers distinct advantages including short fabrication time and low cost as compared to grinding or polishing process. However, the DTM process can leave mid-frequency error in the optical surface which generates an undesirable diffraction effect and stray light. The mid-frequency error is expected to be eliminated by mechanical polishing after the DTM process, but polishing of soft surface of ductile aluminum is extremely difficult because the polishing process inevitably degrades the surface form accuracy. In order to increase its surface hardness, we performed electroless nickel plating on the surface of diamond-turned aluminum (Al-6061T6) off-axis mirrors, which was followed by the 6-hour-long baking process at $200^{\circ}C$ for improving its hardness. Then we polished the nickel plated off-axis mirrors to remove the mid-frequency error and measured polished mirror surfaces using the optical surface profilometer (NT 2000, Wyko Inc.). Finally, we ascertained that the mid-frequency error on the mirror surface was successfully removed. During the whole processes of nickel plating and polishing, we monitored the form accuracy using the ultra-high accurate 3-D profilometer (UA3P, Panasonic Corp.) to maintain it within the allowable tolerance range (< tens of nm). The polished off-axis mirror was optically tested using a visible laser source and a pinhole, and the airy pattern obtained from the polished mirror was compared with the unpolished case to check the influence of mid-frequency error on optical images.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.191-192
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• 2013

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.1507-1508
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• 2011

• 한국전기전자재료학회논문지
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• 제14권1호
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.481-482
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• 2006

Chemical-mechanical polishing, the dominant technology for LSI planarization, is trending to play an important function in micro-electro mechanical systems (MEMS). However, MEMS CMP process has a couple of different characteristics in comparison to LSI device CMP since the feature size of MEMS is bigger than that of LSI devices. Preliminary CMP tests are performed to understand material removal rate (MRR) with blanket wafer under a couple of polishing pressure and velocity. Based on the blanket CMP data, this paper focuses on the consumable approach to enhance MEMS CMP by the adjustment of slurry and pad. As a mechanical tool, newly developed microstructured (MS) pad is applied to compare with conventional pad (IC 1400-k Nitta-Haas), which is fabricated by micro melding method of polyurethane. To understand the CMP characteristics in real time, in-situ friction force monitoring system was used. Finally, the topography change of poly-si MEMS structures is compared according to the pattern density, size and shape as polishing time goes on.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.39-42
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• 2002

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity(WIWNU) were measured as a function of different slurry composition. As a experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows In the first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saving of high costs of slurry.

• 한국정보통신학회논문지
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• 제18권6호
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• pp.1401-1406
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• 2014

반도체소자의 제조 공정 기술 중 구리패턴을 얻기 위해서 사용하는 화학 기계적 연마(CMP)를 이용한 평탄화와 연마 공정에서 Wafer에 도포된 구리의 두께를 실시간으로 측정하여 정밀하게 제어할필요가 있는데, 이때 획득되는 센서값을 실제 두께 값으로 환산하는 계산과정에서 오차가 발생할 수 있다. 실제 측정 값에 근사한 값을 얻도록 단순평균을 이용한 방법, 이동 평균, 필터 들을 사용하여 결과를 비교하여 옹고스트롬 단위의 두께를 실시간으로 측정하는 제어 시스템의 편차를 줄이도록 하는 방법의 구현에 대해 기술한다.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.759-764
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• 2003

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt％ contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.66-66
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• 2007

Lead zirconate titanate (PZT) is one of the most attractive perovskite-type materials for ferroelectric random access memory (FRAM) due to its higher remanant polarization and the ability to withstand higher coercive fields. We first applied the damascene process using chemical mechanical polishing (CMP) to fabricate the PZT thin film capacitor to solve the problems of plasma etching including low etching profile and ion charging. The $0.8{\times}0.8\;{\mu}m$ square patterns of silicon dioxide on Pt/Ti/$SiO_2$/Si substrate were coated by sol-gel method with the precursor solution of PZT. Damascene process by CMP was performed to pattern the PZT thin film with the vertical sidewall and no plasma damage. The polarization-voltage (P-V) characteristics of PZT capacitors and the current-voltage characteristics (I-V) were examined by change of process parameters. To examine the CMP induced damage to PZT capacitor, the domain structure of the polished PZT thin film was also investigated by piezoresponse force microscopy (PFM).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.35-38
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• 2000

In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.l8um semiconductor device. Through reverse moat pattern process, reduced moat density at high moat density, STI CMP process with low selectivity could be to fit polish uniformity between low moat density and high moat density. Because this reason, in-situ motor current end point detection method is not fit to the current EPD technology with the reverse moat pattern. But we use HSS without reverse moat pattern on STI CMP and take end point current sensing signal.[1] To analyze sensing signal and test extracted signal, we can to adjust wafer difference within $110{\AA}$.