• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.9
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• pp.83-88
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• 2014

When DG interconnection into network is examined, details of the review are overvoltage, protective device malfunction, etc. In the case of protective device malfunction, replacing protective device into bi-directional protective device and installation NGR are the solution. Overvoltage at interconnection point occurs because the load is relatively less than DG output. When overvoltage at interconnection point occurs, DG interconnection is not permitted because this overvoltage affect other customers. Interconnection by installation new distribution line is one solution but it costs much money. Without installation new investment, change of NOP(Normal Open Point) position is a possible solution about DG interconnection into network.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.10-15
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• 2016

In this paper, novel ball grid array (BGA) interconnection process using solderable anisotropic conductive adhesives (SACAs) with low-melting-point alloy (LMPA) fillers have been developed to enhance the processability in the conventional capillary underfill technique and to overcome the limitations in the no-flow underfill technique. To confirm the feasibility of the proposed technique, BGA interconnection test was performed using two types of SACA with different LMPA concentration (0 and 4 vol%). After the interconnection process, the interconnection characteristics such as morphology of conduction path and electrical properties of BGA assemblies were inspected and compared. The results indicated that BGA assemblies using SACA without LMPA fillers showed weak conduction path formation such as solder bump loss or short circuit formation because of the expansion of air bubbles within the interconnection area due to the relatively high reflow peak temperature. Meanwhile, assemblies using SACA with 4 vol% LMPAs showed stable metallurgical interconnection formation and electrical resistance due to the favorable selective wetting behavior of molten LMPAs for the solder bump and Cu metallization.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.311-313
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• 2003

There have been public attraction and studies about distributed generation systems. But protective relay must be installed between utility system and customer owned distributed generation system has not been developed. So this paper describes the development of a digital protective relay for interconnection. The developed protective relay includes protective elements required by KEPCO at the interconnection point.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.419-428
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• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.12
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• pp.1705-1710
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• 2018

This paper deals with an analysis of the causes of over current relay(OCR) misoperation in power system with distributed generations(DG). In general, Y-D and Y-Y-D transformer connections are used for grid interconnection of DG. According to the interconnection guideline, the neutral point on Y side should be grounded. However, these transformer connections can lead to OCR misoperation as well as over current ground relay(OCGR) misoperation. Several researches have addressed the OCGR misoperation due to the interaction between transformer connections and zero-sequence voltage of distribution system. Recently, a misoperation of OCR at the point of DG interconnection to the utility system has been also reported. With increasing the interconnections of DG, such OCR as well as OCGR misoperations are expected to increase. In this paper, PSCAD/EMTDC modeling including DG interconnection transformer was performed and various case studies was carried out for identifying the cause of OCR misoperation.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.73-73
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• 2009

In this sutdy, a new class ACA(Anisotropic Conductive Adhesive) with low-melting-point alloy(LMPA) and self-organized interconnection method were developed. This developed self-organized interconnection method are achieved by the flow, melting, coalescence and wetting characteristics of the LMPA fillers in ACA. In order to observe self-interconnection characteristic, the QFP($14{\times}14{\times}2.7mm$ size and 1mm lead pitch) was used. Thermal characteristic of the ACA and temperature-dependant viscosity characteristics of the polymer were observed by differential scanning calorimetry(DSC) and torsional parallel rheometer, respectively. A electrical and mechanical characteristics of QFP bonding were measured using multimeter and pull tester, respectively. Wetting and coalescence characteristics of LMPA filler particles and morphology of conduction path were observed by microfocus X-ray inspection systems and cross-sectional optical microscope. As a result, the developed self-organized interconnection method has a good electrical characteristic($2.41m{\Omega}$) and bonding strength(17.19N) by metallurgical interconnection of molten solder particles in ACA.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.527-529
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• 2001

Interfaces are the point of interconnection between distributed generation and the energy infrastructure. These interfaces are generally physical but can include a market dimension as well. While there are issues surrounding various interfaces, the most important issues in the short term are on the electrical interface. Much of the discussion and debate surrounding distributed generation interconnection has centered on technical issues. However, there are two elements of Interconnection that merit equal consideration-process and contractual issues. The solution of distributed generation Interconnection issues depends on whether existing requirements can be modified to make them more efficient, transparent, and standardized while maintaining the grid's reliability and safety. In this paper, two main courses, standardization and third party participation, are suggested for the resolution of these issues.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1305-1317
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• 1999

NUMA 구조는 원격 메모리에 대한 접근이 불가피한 구조적 특성 때문에 상호 연결망이 성능을 좌우하는 큰 변수가 된다. 기존에 대중적으로 사용되던 버스는 물리적 확장성 및 대역폭에서 대규모 시스템을 구성하는 데 한계를 보인다. 이를 대체하는 고속의 지점간 링크를 사용한 링 구조는 버스가 가지는 확장성 및 대역폭의 한계라는 단점을 개선하였으나, 많은 클러스터가 연결되는 경우에는 전송 지연시간이 증가하는 문제점을 가지고 있다. 본 논문에서는 스누핑 프로토콜이 적용된 링 구조에서 클러스터 개수 증가에 따른 지연시간 증가의 문제점을 보완하기 위해 계층적 링 구조로의 확장을 제안하고, 이 구조에 효과적인 캐쉬 일관성 프로토콜을 설계하였다. 전역 링과 지역 링을 연결하는 브리지는 캐쉬 프로토콜을 관리하며 이 프로토콜에 의해 지역 링의 부하를 줄일 수 있도록 트랜잭션을 필터링하는 역할도 담당함으로써 시스템의 성능을 향상시킨다. probability-driven 시뮬레이터를 통해 계층적 링 구조가 시스템의 성능 및 링 이용률에 미치는 영향을 알아본다. Abstract Since NUMA architecture has to access remote memory, interconnection network performance determines performance of NUMA architecture. Bus, which has been used as popular interconnection network of NUMA, has a limit to build a large-scale system because of limited physical scalability and bandwidth. Ring interconnection network, composed of high-speed point-to-point link, made up for bus's defects of scalability and bandwidth. But, it also has problem of increasing delay as the number of clusters is increased. In this paper, we propose a hierarchical expansion of snoop-based ring architecture in order to overcome ring's defects of increasing delay. And we also design an efficient cache coherence protocol adopted to this architecture. Bridge, which connects local ring and global ring, maintains cache coherence protocol and does snoop-filtering which reduces local ring and cluster bus utilization. Therefore bridge can improve performance of this system. We analyze effects of hierarchical architecture on the performance of system and utilization of point-to-point links using probability-driven simulator.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.2
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• pp.105-115
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• 2002

Since NUMA architecture has to access remote memory an interconnection network determines the performance of CC-NUMA system Bus which has been used as a popular interconnection network has many limits to build a large-scale system because of the limited physical scalabilty and bandwidth Dual ring interconnection network composed of high speed point-to-point links is made up for resolving the defects of the bus for large-scale system But it also has a problem that the response latency is rapidly increased when many node are attached to snooping based CC-NUMA system with dual ring In this paper we propose a chordal ring architecture in order to overcome the problem of the dual ring on snooping based CC-NUMA system and design and efficient link controller adopted to this architecture. We also analyze the effects of chordal ring architecture on the system performance and the response latency by using probability driven simulator.