• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.252-259
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• 1990

This paper present new scheme for a Side Wall Masked Isolation(SWAMI) technology which take all the advatages provided by conventional LOCOS process. A new SWAMI process incorporates a sloped sidewall by reactive ion etch and a layer of thin nitride around the side walls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. As a fabricate results, a defect-free fully recessed zero bird's beak local oxidation process can be realized by the sloped wall anisotropic oxide isolation. No additional masking step is required. The leakage current of PN diodes of this process were reduced than PN diode of conventional LOCOS process. On the other hand, the edge junction part was larger than the flat juction part in the density of leakage current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1990.10a
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• pp.88-90
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• 1990

In this study, PN junction solar cell and P$\^$+/-N-N$\^$+/ BSF solar cell, using N-type(111), 10$\^$16/[atoms/cm$\^$-3/] wafer, were fabricated applying that ion implant method whose dose are 1E14, 1E15, 3E15 and its acceleration energy is 50Key, 100Key respectively. The impurity concentration of two types of front-side are 10$\^$18/[atoms/cm$\^$-3/] and back-side concentration for BSF solar cell is 10$\^$17/[atoms/cm$\^$-3/]. As a result of comparison for 2 typical types of cells out of various fabricated samples, open circuit voltage (Voc), short circuit current(Isc) of BSF solar cell are larger than those of PN solar cell by 48[%], 14[%]. Considering that the efficiency of BSF cell is 2.5[%] as well as PN solar cell's is 7.5[%], 10.0[%] of efficiency improvement effect can be obtained from BSF solar cell. Futhermore, in consequence of front-side impurity concentration change from 10$\^$17/[atoms/cm$\^$-3] to 10$\^$20/[atoms/cm$\^$-3/] alternately, the most ideal result can be expected when it is 10$\^$18/[atoms/cm$\^$-3/].

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1146-1148
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• 1995

To improve the breakdown characteristics of vertical power devices, field limiting ring(FLR) is popularly used. In this paper, at vertical power device having $300{\sim}600V$ breakdown voltage, FLR thecnique is considered, by two dimensional computer simulator, with the various of parameters; number of FLR, seperation distance of first FLR from the main juncton and second FLR from the first FLR, doping concentration and thickness of epi-layer, etc.. Below $40{\mu}m$ epi thickness, and for the case of one FLR, the maximum breakdown voltage, 580V is obtained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.93-97
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• 1990

Interfacil charge approximations and structures at doped semiconductor interfaces were proposed. Rectifying phenomena at the III-V compound semiconductor (p-GaP, p-InP, n-GaAs)/$CsNO_3$ aqueous electrolyte interfaces were qualitatively analyzed in terms of their cyclic current-voltage characteristics. The current-voltage characteristic curves, the ion adsorption and potential barrier processes at the semiconductor interfaces were verified using continuous cyclic voltammetric methods. The pn or np junction structures and the related rectifying types at the doped semi-condudtor-electrolyte inferfaces are determined by the space charges.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• Journal of IKEEE
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• v.28 no.3
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• pp.360-364
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• 2024

Npn heterostructures with GaN collectors were fabricated using nanomembrane (NM) stacking. N- and p-Si NMs were transfer-printed onto the n-GaN substrates, resulting in the formation of vertical n-Si/p-Si/n-GaN heterostructures. Electrical measurements of Si/Si and Si/GaN pn heterostructures exhibited rectifying properties, indicating that the formation of bipolar junctions was feasible through NM stacking. The energy band diagram of stacking-enabled npn heterostructure was analyzed to explain the rectifying behaviors of base-emitter and collector-base junctions, as well as to suggest potential applications for bipolar junction transistors with a GaN subcollector.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.8
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• pp.14-18
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• 2018

Generally. the Ohmic's law is an important factor to increase the conductivity in a micro device. So it is also known that the Ohmic contact in a semiconductor device is import. The PN junction as a structure of semiconductor involves the depletion layer, and this depletion layer induces the non linear electrical properties and also makes the Schottky contact as an intrinsic characteristics of semiconductor. To research the conduction effect of insulators in the semiconductor device, $SiO_2$ thin film and $V_2O_5/SiO_2$ thin film were researched by using the current-voltage system. In the nano electro-magnetic system, the $SiO_2$ thin film as a insulator had the non linear Schottky contact, and the as deposited $V_2O_5$ thin film had the linear Ohmic contact owing to the $SiO_2$ thin film with superior insulator's properties, which decreases the leakage current. In the positive voltage, the capacitance of $SiO_2$ thin film was very low, but that of $V_2O_5$ thin film increased with increasing the voltage. In the normal electric field system, it was confirmed that the conductivity of $V_2O_5$ thin film was increased by the effect of $SiO_2$ thin film. It was confirmed that the Schottky contact of semiconductors enhanced the performance of electrical properties to increased the conductivity.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1347-1348
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• 2008

The efficacy and its degradation of light emitting diode(LED) are related to its PN junction's temperature(Tj). Currently efficacy in certain temperature and thermo-resistant are defined for the depending. However, the definitions are quite inconvenient for lighting application. The paper focuses on the issue and presents a method to evaluate the thermal characteristics of LED efficay.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1369-1374
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• 1989

Electrical characteristics at the p-GaP semiconductor/CsNO3 electrolyte interfaces were investigated. It is found that such interfacial phenomena are well analyzed by semiconductor-semiconductor pn junction diode models and image charge effects of semiconductor-vacuum interfaces. The formation processes of electrical double layers and their potential variations are verified using cyclic voltammetric methods. The interfacial current are influenced by Cs+ ion coverage onto the semiconductor electrode surface and structure of electrical double layer.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.1-5
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• 2012

This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-${\mu}m$ by 200-${\mu}m$ optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-$mm^2$ area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only $120{\mu}W$ in the sleep mode.