• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.1092-1095
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• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• 한국재료학회지
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• 제28권1호
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• pp.38-42
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• 2018

Continuous efforts are being made to improve the efficiency of Si solar cells, which is the prevailing technology at this time. As opposed to the standard front-lit solar cell design, the back-lit design suffers no shading loss because all the metal electrodes are placed on one side close to the pn junction, which is referred to as the front side, and the incoming light enters the denuded back side. In this study, a systematic comparison between the two designs was conducted by means of computer simulation. Medici, a two-dimensional semiconductor device simulation tool, was utilized for this purpose. The $0.6{\mu}m$ wavelength, the peak value for the AM-1.5 illumination, was chosen for the incident photons, and the minority-carrier recombination lifetime (${\tau}$), a key indicator of the Si substrate quality, was the main variable in the simulation on a p-type $150{\mu}m$ thick Si substrate. Qualitatively, minority-carrier recombination affected the short circuit current (Isc) but not the opencircuit voltage (Voc). The latter was most affected by series resistance associated with the electrode locations. Quantitatively, when ${\tau}{\leq}500{\mu}s$, the simulation yielded the solar cell power outputs of $20.7mW{\cdot}cm^{-2}$ and $18.6mW{\cdot}cm^{-2}$, respectively, for the front-lit and back-lit cells, a reasonable 10 % difference. However, when ${\tau}$ < $500{\mu}s$, the difference was 20 % or more, making the back-lit design less than competitive. We concluded that the back-lit design, despite its inherent benefits, is not suitable for a broad range of Si solar cells but may only be applicable in the high-end cells where float-zone (FZ) or magnetic Czochralski (MCZ) Si crystals of the highest quality are used as the substrate.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.406-406
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• 2011

결정질 태양전지에서 도핑(Doping)은 반도체(Semiconductor)의 PN 접합(Junction)을 형성하는 중요한 역할을 한다. 도핑은 반도체에 불순물(Dopant)을 주입하는 공정으로 고온에서 진행되며 온도는 중요한 변수(Parameter)로 작용한다. 본 연구에서는 여러 가지 에미터(emitter)층 형성방법 중에 가장 저가이면서 공정과정이 간단하며 대면적 도핑이 용의한 Spray 방법을 통해 효과적인 에미터 층 형성의 최적화를 위해 DI water에 각각 1%, 3%, 5% 7%로 희석된 H3PO4용액 으로 850$^{\circ}C$에서 열처리 시간을 가변해 가며 최적화된 면저항과 표면농도 특성을 분석하였다. 도핑소스가 웨이퍼(wafer) 각각의 표면에 흡착시킨 후 오븐에 넣어 150$^{\circ}C$에서 5분간 건조시킨 후 퍼니스(furance)에 넣어 시간을 가변해 가며 도핑시켰다. Spray 방식은 기존의 방식보다 저렴하고 In-line 공정에 적합하며 대용량으로 전환이 쉽다는 많은 장점을 가지고 있다. 도핑시 먼저 spray를 이용하여 웨이퍼 표면에 균일하게 용액을 흡착시킨 후 오븐에서 150$^{\circ}C$에서 5분간 건조 후 furnace에 넣어 850$^{\circ}C$에서 시간을 가변 해가며 실험하였다. H3PO4용액의 비율이 1%일 때는 2분 이상 열처리를 하였을 때 60${\Omega}/{\Box}$ 이하로 내려가지 않았다. 이는 최초 표면농도가 낮아 더 이상 확산되지 않음을 의미한다. 또한 H3PO4의 비율이 3% 이상일 때는 열처리 시간이 1분 이하일 때 면저항의 변화가 거의 없었으나 2분 이상일 때는 시간에 따라서 점차 낮아졌으며 균일도 역시 좋아졌다. 이는 H3PO4의 비율이 3% 이상일 때는 표면농도가 높아서 1분 이하의 열처리 시간에서는 확산해 들어가는 양이 거의 같음을 알 수 있었다.

• 한국전기전자재료학회논문지
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• 제29권9호
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• pp.559-564
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• 2016

This study examined the malfunction mode of the HCMOS IC under narrow-band high-power electromagnetic wave. Magnetron is used to a narrow-band electromagnetic source. MFR (malfunction failure rate) was measured to investigate the HCMOS IC. In addition, we measured the resistance between specific pins of ICs, which are exposed and not exposed to the electromagnetic wave, respectively. As a test result of measurement, malfunction mode is shown in three steps. Flicker mode causing a flicker in LED connected to output pin of IC is dominant in more than 7.96 kV/m electric field. Self-reset mode causing a voltage drop to the input and output of IC during electromagnetic wave radiation is dominant in more than 9.1 kV/m electric field. Power-reset mode making a IC remained malfunction after electromagnetic radiation is dominant in more than 20.89 kV/m. As a measurement result of pin-to-pin resistance of IC, the differences between IC exposed to electromagnetic wave and normal IC were minor. However, the five in two hundred IC show a relatively low resistance. This is considered to be the result of the breakdown of pn junction when latch-up in CMOS occurred. Based on the results, the susceptibility of HCMOS IC can be applied to a basic database to IC protection and impact analysis of narrow-band high-power electromagnetic waves.

• 한국전기전자재료학회논문지
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• 제35권3호
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• pp.241-245
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• 2022

In this study, we measured and comparatively analyzed the characteristics of MPS (Merged Pin Schottky) diodes in 4H-SiC by changing the areal ratio between the Schottky and PN junction region. Increasing the temperature from 298 K to 473 K resulted in the threshold voltage shifting from 0.8 V to 0.5 V. A wider Schottky region indicates a lower on-resistance and a faster turn-on. The effective barrier height was smaller for a wider Schottky region. Additionally, the depletion layer became smaller under the influence of the reduced effective barrier height. The wider Schottky region resulted in the ideality factor being reduced from 1.37 to 1.01, which is closer to an ideal device. The leakage saturation current increased with the widening Schottky region, resulting in a 1.38 times to 2.09 times larger leakage current.

• 한국전기전자재료학회논문지
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• 제30권9호
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.143-144
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• 2010

3-5족 화합물 반도체를 이용한 집광형 삼중 접합 태양전지는 40% 이상의 광변환 효율로 많은 주목을 받고 있다[1]. 삼중 접합 태양전지의 하부 셀은 기계적 강도가 높고 장파장을 흡수할 수 있는 Ge이 사용된다. Ge위에 성장될 III-V족 단결정막으로서 Ge과 격자상수가 일치하는 GaInP나 GaAs가 적합하고, 성장 중 V족 원소의 열확산으로 인해 Ge과 pn접합을 형성하게 된다. 이때 GaInP의 P의 경우 GaAs의 As보다 확산계수가 낮아 태양전지 변환효율향상에 유리한 얇은 접합 형성이 가능하고, 표면 에칭효과가 적기 때문에 GaInP를 단결정막으로 선택하여 p-type Ge기판 위 성장으로 단일접합 Ge구조 제작이 가능하다. 하지만 이종접합 구조 성장으로 인해 발생한 계면사이의 전위나 미세결함들이 결정막내부에 존재하게 되며 이러한 결함들은 광학소자 응용 시 비발광 센터로 작용할 뿐 아니라 소자의 누설전류를 증가시키는 원인으로 작용하여 태양전지 변환효율을 감소시키게 된다. 이에 결함감소를 통해 소자의 전기적 특성을 향상시키고자 수소 열처리나 플라즈마 공정을 통해 수소 원자를 박막내부로 확산시키고, 계면이나 박막 내 결함들과 결합시킴으로서 결함들의 비활성화를 유도하는 연구가 많이 진행되어 왔다 [2][3]. 하지만, 격자불일치를 갖는 GaInP/Ge 구조에 대한 수소 열처리 및 불순물 준위의 거동에 대한 연구는 많이 진행되어 있지 않다. 따라서 본 연구에서는 Ga0.45In0.55P/Ge구조에 수소 열처리 공정을 적용을 통하여 단결정막 내부 및 계면에서의 결함밀도를 제어하고 이를 통해 태양 전지의 변환효율을 향상시키고자 한다. <111> 방향으로 $6^{\circ}C$기울어진 p-type Ge(100) 기판 위에 유기금속화학증착법 (MOCVD)을 통해 Si이 도핑된 200 nm의 n-type GaInP층을 성장하여 Ge과 단일접합 n-p 구조를 제작하였다. 제작된 GaInP/Ge구조를 furnace에서 250도에서 90~150분간 시간변화를 주어 수소열처리 공정을 진행하였다. 저온 photoluminescence를 통해 GaInP층의 광학적 특성 변화를 관찰한 결과, 1.872 eV에서 free-exciton peak과 1.761 eV에서 Si 도펀트 saturation에 의해 발생된 D-A (Donor to Acceptor)천이로 판단되는 peak을 검출할 수 있었다. 수소 열처리 시간이 증가함에 따라 free-exciton peak 세기 증가와 반가폭 감소를 확인하였고, D-A peak이 사라지는 것을 관찰할 수 있었다. 이러한 결과는 수소 열처리에 따른 단결정막 내부의 수소원자들이 얕은 불순물(shallow impurity) 들로 작용하는 도펀트들이나, 깊은 준위결함(deep level defect)으로 작용하는 계면근처의 전위, 미세결함들과의 결합으로 결함 비활성화를 야기해 발광세기와 결정질 향상효과를 보인 것으로 판단된다. 본 발표에서는 상술한 결과를 바탕으로 한 수소 열처리를 통한 박막 및 계면에서의 결함준위의 거동에 대한 광분석 결과가 논의될 것이다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.