• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.29-34
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• 2016

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

• The KIPS Transactions:PartB
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• v.13B no.4 s.107
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• pp.429-438
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• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.

• International Journal of Advanced Culture Technology
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• v.9 no.4
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• pp.282-287
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• 2021

A multicore system must be able to take full advantage of the program's instruction and data parallelism. This study introduces the data replication technique as a support technique to maximize the program's instruction and data parallelism. Instruction level parallelism can be limited by data dependency. In this case, if data is replicated to each processor core and used, instruction level parallelism can be used to the maximum. The technique proposed in this study can maximize the performance improvement effect when applied to scientific applications such as matrix multiplication operation.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.517-530
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• 1994

In this paper, design of small microprocessor unit is implemented using research purpose VHDL and CAD tools by top-down design method. For this, original basic MPU and its pipelining architectures are suggested. Once, design target, instruction sets, architecture are decided, the operation is confirmed by C language simulation, and then the operation is confirmed by checking internal register contents for given inputs in the case of VHDL simulation. Then, design layouts are made by full/semi-custom design methods by research CAD tools and related simulation is implemented. The feasibility of suggested pipelined structure for performance improvement is confirmed by simulation, and related problems and future research directions are discussed. In conclusion, the MPU design methodology is set up and the design change of architecture is possible by this paper.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.51-54
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically Parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56309. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• Speech Sciences
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• v.7 no.2
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• pp.225-234
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(Code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56362. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.2
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• pp.153-158
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• 1992

We propose, in this paper, a new thinning algorithm and demonstrate Its effectiveness with some concrete experimental results. This new thinning process can solve the problems of disconnectivity and end point reduction explored in one-Pass algorithm Furthermore, this algorithm is proven effective particularly In high speed operation. A processor for this algorithm that is capable of hand-ling Input Image width(between 25 and 4t) bits ) and also operates on pipelining, is implemented and tested. Flexibility and high speed operation of this thinning processor should find excellent applicability in various areas.