• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.6
• /
• pp.717-726
• /
• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2301-2306
• /
• 2015

The time to address the exabytes of data has come as the information age accelerates. Big data transfer technology is essential for processing large amounts of data. This paper posits to transfer big data in the optimal conditions by the proposed algorithm for predicting the optimal combination of Pipelining, Concurrency, and Parallelism (PCP), which are major functions of GridFTP. In addition, the author introduced a simple design process of Takagi-Sugeno-Kang (TSK) fuzzy model and designed a model for predicting transfer throughput with optimal combination of Pipelining, Concurrency and Parallelism. Hence, the author evaluated the model of the proposed algorithm and the TSK model to prove the superiority.

• Journal of KIISE
• /
• v.42 no.3
• /
• pp.281-288
• /
• 2015

A volcano disaster damage prediction system supports decision making for counteracting volcanic disasters by simulating meteorological condition and volcanic eruptions. In this system, a program called Fall3D generates predicted results for the diffusion of ash after a volcanic eruption on the basis of meteorological information. The relevant meteorological information is generated by a weather numerical prediction model known as Weather Research & Forecasting (WRF). In order to reduce the entire processing time without modifying these two simulation programs, pipelining can be used by partly executing Fall3D whenever the hourly (partial) results of WRF are generated. To reduce the processing time, successor programs such as Fall3D require that certain features be suspended until the part of the results that is based on prior calculation is generated by a predecessor. Even though Fall3D does not have a suspend or resume feature, pipelining effect can be produced by using the program's restart feature, which resumes simulation from the previous session. In this study, we suggest a workflow that can control the execution type.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.12
• /
• pp.2409-2417
• /
• 1994

The ODR(orthogonal double-rotation) digital lattice filters have desirable properties for VLSI implementation such as local connection, regularity and pipelinability. These filters are also known to exhibit good numerical behavior for finite precision implementation. Although these filters can be pipelined by the cut-set localization procedure, it should be noted that the maximum sample rate obtained by this technique is limited by the feedback computations. In this paper, a pipelining method for the ODR digital lattice filter is proposed, by which the sample rate can be increased at any desired level. it is also shown that the low-power CMOS digital implementation of ODR digital lattice filters can be done successfully using our pipelining method. The pipelining method is based on the properties of the Schur algoithm, constrained filter design methods, and the polyphase decomposition technique.

• Journal of the Korea Society for Simulation
• /
• v.26 no.3
• /
• pp.13-22
• /
• 2017

This research proposes and applies a pipelining parallel processing technique to enhance the speed of visualizing the results of real-time simulations. Generally, a simulation with real-time visualization consists of three processes: executing a simulation model, transmitting simulation result, and visualizing simulation result. If we have these processes in serial, the latency from simulation to visualization will be very long, which degrades the speed of visualization of data from real-time simulation. Thus, the main purpose of this research is maximizing performance by adapting pipelining parallel processing technique to the real-time simulation visualization. Also we show that performance is improved by adding multi-threading technique to each process. This paper proposes a theoretical performance model and simulation results of the techniques and then we applied this to an air combat simulation model as a case study. As the result, it shows that the performance is greatly enhanced than the original model's execution time.

• 전기의세계
• /
• v.31 no.11
• /
• pp.775-786
• /
• 1982

Bit-slice 마이크로프로세서의 구조를 설명하고, bit-slice시스템의 설계를 위해 필요한 마이크로 인스트럭숀의 구성과 pipelining 기법에 관해 토의한다.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.10
• /
• pp.13-26
• /
• 1993

Motion picture algorithms are realized on the multiprocessor system presented in the Study I. For the most efficient processing of the algorithms, pipelining and geometrical parallel processing methods are employed, and processing time, communication load and efficiency of each algorithm are compared. The performance of the implemented system is compared and analysed with reference to MPEG coding algorithm. Theoretical calculations and experimental results both shows that geometrical partitioning is a more suitable parallel processing algorithm for moving picture coding having the advantage of easy algorithm modification and expansion, and the overall efficiency is higher than pipelining.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.1
• /
• pp.29-34
• /
• 2016

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.727-730
• /
• 1998

In this paper, we propose an implementation of an efficient parallel Radon transform on TMS320C80-based system. For an N$\times$N SAR image, we can obtain O(NM/p) of the conventional parallel Radon transform, by representing the projection patterns in Radon space variables instead of the image space variables, and pipelining the algorithm, where p is the number of processors and M is the number of projection angles. Also, we can reduce the time for the dynamic load distribution among the nodes and the communication overheads of accessing the global memories, by pipelining the memory and processing operations by using tripple buffer structure. Experimental results show an efficient parallel Radon transform of speedup Sp=3.9 and efficiency E=97.5% for 256$\times$256 image, when implemented on TMS320C80 composed of four parallel slave processors with three memory blocks.

• Proceedings of the Acoustical Society of Korea Conference
• /
• autumn
• /
• pp.53-56
• /
• 2004

본 논문은 HMM 기반 임베디드 음성인식 시스템 구현에 관한 몇 가지 주제들을 설명한다. 임베디드 환경은 한정된 자원을 가지고 있고 그러한 가운데 타당한 인식률과 향상된 인식 속도를 얻기 위해서 몇가지 방법들을 이 논문에서 설명한다. 구현 환경은 DSP6711 기반에서 이루어졌다. 가우시안 mixture 계산 루틴을 부동소수점 연산에서 고정소수점 연산 및 software pipelining을 적용하였다. 고정소수점 변환 전과 후 비슷한 인식률을 얻었고 고정소수점 변환과 software pipelining 적용 후 연산 속도의 향상을 얻었다.