• 한국통신학회논문지
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• 제22권3호
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• pp.444-453
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• 1997

This paper presents the prototype design of hardware/software cosynthesis system for pipelined application-specific instruction processors. Taking application programs in VHDL as inputs, the proposed system generates a pipelined instruction-set processor and the instruction sequences running on the generated machine. The design space of datapath and controller is defined by the architectural templates embedded in the system. Generating the intyermediate code adequate for parallelism analysis and extraction, the system converts it into assembly codes. Experimental results show the effectiveness of the proposed system.

• 전자공학회논문지C
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• 제36C권3호
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• pp.1-7
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• 1999

본 연구에서는 파이프라인 구조를 갖는 시스템의 효율적인 설계를 위하여 변환을 이용한 설계 최적화 기술을 개발하였다. 변환 최적화 기술은 파이프라인 구조로의 변환과 retiming을 이용한 변환을 포함한다. 새로운 변환 방법은 다음의 세 가지 특징을 갖는다. 첫째, 여러 개의 파이프라인 블록을 동시에 고려하여 retiming 등의 변환을 수행함으로써, 파이프라인 구조 시스템의 전체 성능을 최적화한다. 둘째, 시스템의 면적과 수행시간 간의 trade-off를 가능하도록 하여, 회로 설계자가 다양한 설계의 대안을 찾고자 할 때 실용적인 도움을 준다. 셋째, 본 방법은 새로운 변환 및 알고리즘 개발 등의 문제로 쉽게 확장 가능하고, 메모리 또는 버스 등을 고려한 최적화 문제에도 사용될 수 있다. DSP 예제들에 대하여 실험한 결과, 평균적으로 면적은 21%, 성능은 17% 개선되었다. 특히, 본 기술은 여러 설계 대안의 효율적인 탐색에 유용하다.

• 전자공학회논문지B
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• 제33B권9호
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• pp.70-79
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• 1996

Block data transfer poses a serious problem is a pipelined bus where each data transfer step is pipelined. In this paper, we describe the design and implementation of a variable data block transfer protocol for a pipelined bus of a shared-memory multiprocessor. The proposed method maintains compatibility with the existing protocol for the pipelined bus and ensures fairness and effectiveness by preventing starvation. We present flow charts of requester and responder during a block transfer in the pipelined bus that uses the proposed protocol. The proposed protocol was implemented for the TICOM-III HiPi+Bus.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.225-228
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• 2008

In this paper, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features: composite field arithmetic SubByte, efficient MixColumn transformation, and On-the-Fly Key-Scheduling for fully pipelined architecture. By pipelining the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the On-the-Fly key scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• ETRI Journal
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• 제27권5호
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• pp.533-538
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• 2005

We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.939-942
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• 2003

Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.718-727
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• 2014

In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a $0.35{\mu}m$ CMOS standard cell library.

• 대한전자공학회논문지
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• 제25권8호
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.69-72
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• 2002

This paper proposed a new charge-shared switching MDAC for a pipelined A/D converter The proposed architecture accomplishes the same function of a conventional multiplying-digital-to-analog converter (MDAC). By adopting the proposed scheme, about 40% of the total capacitances could be reduced and the speed of the MDAC increases. The performance of the charge-shared switching MDAC has been Proved by HSPICE simulations.