• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.82-92
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• 2001

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

• Journal of Korea Society of Industrial Information Systems
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• v.4 no.2
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• pp.44-50
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• 1999

This paper presents a set of techniques to automatically find rate optimal or near rate optimal implementation of shift-invariant flow graphs on pipelined processor, in which pipeline processor has multiple accumulators and internal datapaths. In such case, the problem to be addressed is the scheduling of multiple instruction streams which control all of the pipeline stages. The goal of an automatic scheduler in this context is to rearrange the order of instructions such that they are executed with minimum iteration period between successive iteration of defining flow graphs. The scheduling algorithm described in this paper also focuses on the problem of removing the hazards due to inter-instruction dependencies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.270-276
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• 2018

Apache Spark is one of the high performance in-memory computing frameworks for big-data processing. Recently, to improve the performance, general-purpose computing on graphics processing unit(GPGPU) is adapted to Apache Spark framework. Previous Spark-GPGPU frameworks focus on overcoming the difficulty of an implementation resulting from the difference between the computation environment of GPGPU and Spark framework. In this paper, we propose a Spark framework based on a heterogenous pipeline computing with OpenCL to further improve the performance. The proposed framework overlaps the Java-to-Native memory copies of CPU with CPU-GPU communications(DMA) and GPU kernel computations to hide the CPU idle time. Also, CPU-GPU communication buffers are implemented with switching dual buffers, which reduce the mapped memory region resulting in decreasing memory mapping overhead. Experimental results showed that the proposed Spark framework based on a heterogenous pipeline computing with OpenCL had up to 2.13 times faster than the previous Spark framework using OpenCL.

• Journal of Korea Society of Industrial Information Systems
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• v.28 no.5
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• pp.89-108
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• 2023

This study provides a comprehensive analysis of recent studies conducted on the topic of nowcasting in order to enhance the accuracy and promptness of official statistical data. Furthermore, we propose an alternative approach involving the utilization of real-time data and its corresponding collection methods to effectively operate a real-time nowcasting model capable of accurately capturing the current economic condition. We explore high-frequency real-time data that can predict economic indicators in both the public and private sectors and propose a pipeline for data collection processing and modeling that is based on cloud platforms. Furthermore we validate the essential elements required for the implementation of real-time nowcasting, as well as their data management protocols to ensure the reliability and consistency needed for accurate forecasting of official statistical indicators.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Journal of Korea Water Resources Association
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• v.46 no.4
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• pp.389-400
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• 2013

In this study, a conventional pipeline unsteady friction model has been integrated into Levenberg Marquardt method to calibrate friction coefficient in a pipeline system. The method of characteristics has been employed as the modeling platform for the frequency dependant model of unsteady friction. In order to obtain Hessian and Jacobian matrix for optimization, the direct differentiation of pressure to friction factor was calculated and sensitivities to friction for heads and discharges were formulated for implementation to the integration constant in the characteristic method. Using a hypothetical simple pipeline system, time series of pressure, introduced by a sudden valve closure, were obtained for various Reynolds numbers. Convergency in fiction factors were evaluated both in steady and unsteady friction models. The comparison of calibration performance between the proposed method and genetic algorithm indicates that faster and stabler behaviour of Levenberg Marquardt method than those of evolutionary calibration.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04b
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• pp.586-588
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• 2001

최근에는 순환 신경망의 생성모델이 비교사 학습에 관련하여 활발히 연구되고 있다. 이러한 형태의 신경망은 형태 추출이나 인식에 효과적으로 사용될 수 있는 반면 반복 loop를 사용하므로 대단히 많은 계산이 필요하다. 본 논문에서는 Oh와 Seung에 의해 제안된 상향전파(Up-propagation) network이라는 순환 신경망을 FPGA를 이용해서 구현하였다. 단층 신경망은 9개의 상층 neuron과 256개의 하층 neuron으로 구성되 있으며 4만 게이트의 FPGA 하나로 효과적으로 구현할 수 있다. pipeline된 곱셈기로 게산 속도를 향상시켰고 sigmoid 전달 함수는 유한 정밀도의 2차 다항식으로 근사될 수 있다. 구현된 하드웨어는 hand-written 숫자 영상인 USPS data를 재생하는데 사용되었으며 좋은 결과를 얻었다.