• The KSFM Journal of Fluid Machinery
• /
• v.14 no.3
• /
• pp.5-9
• /
• 2011

Butterfly valves are widely used in current industry to control the fluid flow. They are used for both on-off and throttling applications involving large flows at relatively low pressure-drop especially in large size pipelines. In this study, we carried out the structure analysis of the butterfly valve components according to pressure testing of the industrial standard. the numerical simulation was performed by using ANSYS Workbench. The reliability of valve is evaluated under the investigation of the strain rate, the leak test and the durability of the valve.

• Computers and Concrete
• /
• v.20 no.6
• /
• pp.671-682
• /
• 2017

In this research, seismic response of pipes is examined by applying nanotechnology and piezoelectric materials. For this purpose, a pipe is considered which is reinforced by carbon nanotubes (CNTs) and covered with a piezoelectric layer. The structure is subjected to the dynamic loads caused by earthquake and the governing equations of the system are derived using mathematical model via cylindrical shell element and Mindlin theory. Navier-Stokes equation is employed to calculate the force due to the fluid in the pipe. Mori-Tanaka approach is used to estimate the equivalent material properties of the nanocomposite and to consider the effect of the CNTs agglomeration on the scismic response of the structure. Moreover, the dynamic displacement of the structure is extracted using harmonic differential quadrature method (HDQM) and Newmark method. The main goal of this research is the analysis of the seismic response using piezoelectric layer and nanotechnology. The results indicate that reinforcing the pipeline by CNTs leads to a reduction in the displacement of the structure during an earthquake. Also the negative voltage applied to the piezoelectric layer reduces the dynamic displacement.

• Journal of the Society of Naval Architects of Korea
• /
• v.55 no.4
• /
• pp.289-296
• /
• 2018

The offshore subsea platforms are connected to subsea pipelines to transport gas/oil from wells. The pipe is a multilayered structure of polymer and steel for compensating both flexibility and strength. The pipe also requires reinforcement structures to endure the extreme environmental conditions. A vertebrae structure of bend restrictors is one of the reinforcement structures installed to protect the subsea pipe from excessive bending deformations. In this study, structural behaviors of the subsea pipeline with bend restrictors are investigated by the multi-body contact analysis in Abaqus 6.14-2. Contact forces of each bend restrictor extracted from the multi-body contact analysis can be boundary conditions for topology design optimization in Altair Hyperworks 13.0 Hypermesh-Optistruct. Multiple design constraints are considered to obtain a manufacturable design with efficient material usage. Through the multi-body contact analysis with optimized bend restrictors, it is confirmed that the bending performance of the optimized design is enhanced.

• The KIPS Transactions:PartC
• /
• v.14C no.4
• /
• pp.383-388
• /
• 2007

In this paper, we propose a new signal frame structure based on Alamouti code that can maintain the same performance as Alamouti code and increase spectral efficiency. The proposed signal frame structure can increase spectrum efficiency to approach 1(bit/s/Hz) since it can process n bit data during (n+1) time slot. In order to verify two performances, we derive closed form BER via mathematical approach, and compare with the simulation result in Rayleigh fading plus AWGN channel. Then we find that the two performances are exactly same.

• Journal of Ocean Engineering and Technology
• /
• v.29 no.3
• /
• pp.207-216
• /
• 2015

Amanifold is one of the essential subsea oil and gas production components to simplify the subsea production layout. It collects the production fluid from a couple of wellheads, transfers it to onshore or offshore storage platforms, and even accommodates water and gas injection flowlines. This paper presents the basic design procedure for a manifold frame structure with novel structural verification using in-house unity check codes. Loads and load cases for the design of an SIL 3 class-manifold are established from a survey of relevant industrial codes. The basic design of the manifold frame is developed based on simple load considerations such as the self weights of the manifold frame and pipeline system. In-house software with Eurocode 3 embedded, called INHA-SOLVER, makes it possible to carry out code checks on the yield and buckling unities. This paper finally proves that the new design of the manifold frame structure is effective to resist a permanent and environment load, and the in-house code is also adaptively combined with the commercial finite element code Nastran.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.1 s.307
• /
• pp.101-108
• /
• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.12
• /
• pp.44-55
• /
• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.71-80
• /
• 2004

This paper describes embedded processor architecture design which is applicable to multimedia in mobile platform The main description is based on basic processor architecture and consideration about energy efficiency when used in mobile platform To design processor data path architecture (pipeline, branch prediction, multiple issue superscalar, function unit number) which is optimal to multimedia application and cache hierarchy and its structure, we have nut the simulation with variant architecture using MPEG4 test bench as multimedia application. We analyzed energy efficiency of architecture to check if it is applicable to mobile platform and decide basic processor architecture based on analysis result. The suggested basic processor architecture not only can be applied to mobile platform but also can be applied to basic processor architecture of configurable processor which is designed through automatic design environment.

• The KIPS Transactions:PartB
• /
• v.9B no.6
• /
• pp.715-726
• /
• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• Journal of Korea Multimedia Society
• /
• v.15 no.10
• /
• pp.1247-1256
• /
• 2012

There are many filter based image processing algorithms and they usually require a huge amount of computations and memory accesses making it hard to attain a real-time performance, expecially in embedded applications. In this paper, we propose a pipelined hardware structure of the filter based face detection algorithm to show that the real time performance can be achieved by hardware design. In our design, the whole computation is divided into three pipeline stages: resizing the image (Resize), Transforming the image (ICT), and finding candidate area (Find Candidate). Each stage is optimized by considering the parallelism of the computation to reduce the number of cycles and utilizing the line memory to minimize the memory accesses. The resulting hardware uses 507 KB internal SRAM and occupies 9,039 LUTs when synthesized and configured on Xilinx Virtex5LX330 FPGA. It can operate at maximum 165MHz clock, giving the performance of 108 frame/sec, while detecting up to 20 faces.