• Transactions on Electrical and Electronic Materials
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• 제7권1호
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.308-309
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• 2016

Reducing surface recombination is a critical factor for high efficiency silicon solar cells. The passivation process is for reducing dangling bonds which are carrier. Tunnel oxide layer is one of main issues to achieve a good passivation between silicon wafer and emitter layer. Many research use wet-chemical oxidation or thermally grown which the highest conversion efficiencies have been reported so far. In this study, we deposit ultra-thin tunnel oxide layer by PECVD (Plasma Enhanced Chemical Vapor Deposition) using $N_2O$ plasma. Both side deposit tunnel oxide layer in different RF-power and phosphorus doped a-Si:H layer. After deposit, samples are annealed at $850^{\circ}C$ for 1 hour in $N_2$ gas atmosphere. After annealing, samples are measured lifetime and implied Voc (iVoc) by QSSPC (Quasi-Steady-State Photo Conductance). After measure, samples are annealed at $400^{\circ}C$ for 30 minute in $Ar/H_2$ gas atmosphere and then measure again lifetime and implied VOC. The lifetime is increase after all process also implied VOC. The highest results are lifetime $762{\mu}s$, implied Voc 733 mV at RF-power 200 W. The results of C-V measurement shows that Dit is increase when RF-power increase. Using this optimized tunnel oxide layer is attributed to increase iVoc. As a consequence, the cell efficiency is increased such as tunnel mechanism based solar cell application.

• 태양에너지
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• 제17권1호
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• pp.59-66
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• 1997

개방전압과 단락전류와 같은 태양전지 출력변수들은 접합깊이, 도핑농도, 금속접합 및 태양전지구조에 의한 변수들이다. 태양전지 설계의 중요한 요소로서 인이 도핑된 에미터와 금속사이의 금속접합은 일함수 차이가 작아 낮은 직렬저항을 가져야 한다. PESC 태양전지는 금속 접합장벽 전극으로 티타늄을 사용한다. 새로운 접합장벽 전극물질로 티타늄과 일함수가 비슷하지만 전기전도도가 우수한 크롬은 금속 접합장벽 전극으로 유망한 금속이다. 티타늄은 일함수 차가 작지만, 접합장벽으로 크롬은 태양전지 제조시 티타늄보다 우수한 전기적 특성들을 갖는다. 본 논문에서는 실리콘 태양전지의 접합장벽 금속전극의 특성을 비교 분석하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.1033-1036
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• 2002

Wafer bonding methods such as fusion and anodic bonding suffer from high temperature treatment, long processing time, and possible damage to the micro-scale sensor or actuators. In the localized bonding process, beating was conducted locally while the whole wafer is maintained at a relatively low temperature. But previous research of localized heating has some problems, such as non-uniform soldering due to non-uniform heating and micro crack formation on the glass capsule by thermal stress effect. To address this non-uniformity problem, a new heater configuration is being proposed. By keeping several points on the heater strip at calculated and constant potential, more uniform heating, hence more reliable wafer bonding could be achieved. The proposed scheme has been successfully demonstrated, and the result shows that it will be very useful in hermetic packaging. Less than 0.2 ㎫ contact Pressure were used for bonding with 150 ㎃ current input for 50${\mu}{\textrm}{m}$ width, 2${\mu}{\textrm}{m}$ height and 8mm $\times$ 8mm, 5mm$\times$5mm, 3mm $\times$ 3mm sized phosphorus-doped poly-silicon micro heater. The temperature can be raised at the bonding region to 80$0^{\circ}C$, and it was enough to achieve a strong and reliable bonding in 3minutes. The IR camera test results show improved uniformity in heat distribution compared with conventional micro heaters. For gross leak check, IPA (Isopropanol Alcohol) was used. Since IPA has better wetability than water, it can easily penetrate small openings, and is more suitable for gross leak check. The pass ratio of bonded dies was 70%, for conventional localized heating, and 85% for newly developed FP scheme. The bonding strength was more than 30㎫ for FP scheme packaging, which shows that FP scheme can be a good candidate for micro scale hermetic packaging.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.254-254
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• 2011

현재 AMLCD(Active Matrix Liquid Crystal Display)는 노트북, 컴퓨터, TV등 여러 영상매체에 있어 가장 많이 활용되고 있는 디스플레이로 손꼽힌다. AMLCD에 구동소자로 사용되는 a-Si:H TFT는 낮은 제조비용과 축적된 기술을 바탕으로 가장 많이 쓰이고 있다. 특히 a-Si이 가지는 소형화나 대형화의 편의성은 모바일 기기, projection TV, 광고용 패널 등 적용분야가 점점 넓어지고 있는 추세이다. 하지만 a-Si라는 물질 자체가 가지는 낮은 이동도는 더 많은 application을 위해 해결되어야 할 과제이다. 낮은 이동도는 a-Si 실리콘 원자간 결합의 불규칙성 및 무질서와 dangling bond에 의한 localize state(deep trap, band tail)의 존재 때문에 발생하며 결과적으로 TFT 소자의 특성의 저하를 가져온다. 앞선 연구에서는 carrier이동도의 개선을 위해서 첫 번째로 insulator층과 active층 사이의 계면 상태를 향상시키기 위해 insulator로 쓰이는 a-SiN층 표면에 0~18 sccm의 유량으로 phosphorus를 주입하였다. AFM분석을 해본 결과 phosphorus를 주입함으로써 계면의 roughness가 줄어드는 것을 확인 할 수 있었다. 이러한 계면의 roughness 감소는 표면 산란(surface scattering)및 전자 포획(trap)의 영향을 줄임으로써 이동도의 향상을 가져왔다. 두 번째로 active층으로 쓰이는 a-Si:H 층의 표면에 phosphorus를 0?9sccm의 유량으로 doping하였다. 이로 인해 channel이 형성되는 active 영역에 직접적으로 불순물을 doping됨으로써 전도도를 증가되어 이동도를 향상시켰다. 하지만 지나친 doping은 불순물 산란(impurity scattering)의 증가로 인해 이동도를 저하시키는 결과를 보여 주었다. 본 연구에서는 TFT의 이동도 향상을 위해 두 가지의 technology를 함께 적용시켜 a-SiN/a-Si:H 계면 각각에 phosphorus를 주입 및 doping을 하였다. 모든 박막은 PECVD로 제작하였으며 각 박막의 두께는 a-SiN/a-SiN(phosphorus)/a-Si:H(doped)/a-Si:H/n+ a-Si($2350{\AA}/150{\AA}/150{\AA}/1850{\AA}/150{\AA}$)으로 고정하고 유량을 변화시키면서 특성을 관찰하였다.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
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• pp.245-248
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• 2011

Many researches have been carried out to improve light absorption in the crystalline silicon solar cell fabrication. The rear reflection is applied to increase the path length of light, resulting in the light absorption enhancement and thus the efficiency improvement mainly due to increase in short circuit current. In this paper, we manufactured the silicon solar cell using the mono crystalline silicon wafers with $156{\times}156mm^2$, 0.5~3.0 ${\Omega}{\cdot}cm$ of resistivity and p-type. After saw damage removal, the dielectric film ($SiN_x$)on the back surface was deposited, followed by surface texturing in the KOH solution. It resulted in single-side texturing wafer. Then the dielectric film was removed in the HF solution. The silicon wafers were doped with phosphorus by $POCl_3$ with the sheet resistance 50 ${\Omega}/{\Box}$ and then the silicon nitride was deposited on the front surface by the PECVD with 80nm thickness. The electrodes were formed by screen-printing with Ag and Al paste for front and back surface, respectively. The reflectance and transmittance for the single-sided and double-sided textured wafers were compared. The double-sided textured wafer showed higher reflectance and lower transmittance at the long wavelength region, compared to single-sided. The completed crystalline silicon solar cells with different back surface texture showed the conversion efficiency of 17.4% for the single sided and 17.3% for the double sided. The efficiency improvement with single-sided textured solar cell resulted from reflectance increase on back surface and light absorption enhancement.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.110-113
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• 1992

$n^{+}$-p homojunction InP diodes were fabricated using thermal diffusion of Sulfur into p-type InP substrates(Zn doped, LEC grown, p=2.3${\times}$10$^{16}$c $m^{-3}$). The Sulfur diffusion was carried out at 550$^{\circ}C$, 600$^{\circ}C$, 700$^{\circ}C$ for 4 hours in a sealed quartz ampule(～2ml in volume) containing 5mg I $n_2$ $S_3$ and Img of red phosphorus. The formed junction depth was below 0.5$\mu\textrm{m}$. After the removal of diffused layer on the rear surface of the wafer, the beak ohmic contacts to the p-side were made with a vacuum evaporation of An-Zn(2%) followed by an annealing at 450$^{\circ}C$ for 5 minutes in flowing Ar gas. The front contacts were made with a vacuum evaporation of Au-Ge(12%) followed by an annealing at 500$^{\circ}C$ for 3 minutes in flowing Ar gas. The remarkable sprctral response of the cells obtained at the region of 6000-8000${\AA}$ region. The open circuit voltage $V_{oc}$ , short circuit current density $J_{sc}$ , fill factor and conversion efficiency η of the fabricated pattern solar cells(diffusion condition : at 700$^{\circ}C$ for 4 hours) were 0.660V, 14.04㎃/$\textrm{cm}^2$, 0.6536 and 10.09%, respectively.y.

• 마이크로전자및패키징학회지
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• 제10권2호
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• pp.1-5
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• 2003

기존 형상의 미세 가열기를 이용한 마이크로 시스템 패키징의 문제점을 해결하기 위해 새로운 형상의 미세 가열기를 제작하여 패키징 실험을 시행하였다. 기존 형상의 미세 가열기와 새로운 미세 가열기의 형상을 각각 제작하여 접합시에 미세 가열기에 발생하는 열분포를 IR카메라를 이용하여 실험하였다. 기존 형상의 미세 가열기가 불균일하게 가열되는 반면, 새로운 형상의 미세 가열기는 매우 균일하게 가열되는 형상을 나타내었고, IR 카메라를 이용한 실험 결과를 바탕으로 각기 다른 형상의 미세 가열기를 이용하여 접합 실험을 실시하였다. 접합 실험시 사용한 미세 가열기는 폭 $50{\mu}m$, 두께 $2{\mu}m$로 제작하였으며, 0.2Mpa 의 압력을 Pyrex glass cap에 가한 상태에서 150mA의 전류를 공급하여 접합을 완료하였다. 접합이 완료된 시편들에 대해서 IPA를 통한 leakage check실험을 실시하였으며, 기존 형상의 미세 가열기를 이용한 시편들은 66%가 테스트를 통과한 반면 새로운 형상의 미세 가열기를 이용한 시편들은 85%이상이 테스트를 통과하였다. Leakage 실험을 통과한 각각의 시편들에 대해서 접합력 측정을 실시한 결과, 기존 형상의 미세 가열기를 이용한 시편들은 15∼21Mpa의 접합력을 나타내었고, 새로운 형상의 미세 가열기를 이용한 시편들은 25∼30Mpa의 우수한 접합력을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.