• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.1018-1023
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• 1998

This paper presents an effective control scheme incorporated in the voltage-fed half-bridge series resonant inverter for induction heating applications, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuit. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching0 operation in spite of sensitive load parameters variation as well as power regulation, specially in the non-magnetic heating loads. The simulation results and the performance characteristics in the steady-state are shown as compared with the experimental results for a prototype induction cooking system rated at 1.2kW.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.985-987
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• 2004

Switched Reluctance Motor(SRM) drive system is known to provide good torque characteristics and high efficiency drive. However, speed variation caused by higher torque ripple is one of main drawback. The Phase-Locked Loop (PLL) technique in conjunction with dynamic dwell angle control has good speed regulation characteristics. In this paper, appropriate advance angle control for high efficiency drive and PLL technique for accurate speed control is proposed. A TMS320F240 DSP is used to realize this drive system. Test results show that the system has good dynamic and precise speed control ability as well as high efficiency.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1150-1159
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• 2017

Flexibility in the power control of ultrasonic transducers has remained a challenge for cleaning applications. This paper introduces a modification of the existing piezoelectric ceramic transducer (PCT) circuit to increase the range of operation through its impedance characteristics. The output power is controlled using the asymmetrical voltage-cancellation (AVC) method. Together with a phase-locked loop control, the switching frequency of the inverter is automatically adjusted to maintain a lagging phase angle under load-parameter variations during the cleaning process. With the proposed modification, the region of the zero-voltage switching (ZVS) operation is extended, which results in a wider range of output power control. A hardware prototype is constructed and the control algorithm is implemented using an STM32F4 microcontroller. Simulation and experimental results are provided to verify the proposed method for a 50-W PCT. The operating frequency and output power ranges under study are 37 - 41 kHz and 15.8 - 50 W, respectively.

• Journal of Power Electronics
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• v.7 no.2
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• pp.97-108
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• 2007

This paper describes simple control structures for a vector controlled stand-alone induction generator (IG) for use under variable speeds. Different control principles, indirect vector control and deadbeat current control, are developed for a voltage source PWM converter and the three-phase variable speed squirrel-cage IG to regulate DC-link and generator voltages with a newly designed phase locked loop circuit. The required reactive power for the variable speed IG is supplied by means of a PWM converter and a capacitor bank to buildup the voltage of the IG without the need for a battery, to reduce the rating of the PWM converter while using only three sensors and to eliminate the harmonics generated by the PWM converter. These proposed schemes can be used efficiently for variable speed wind energy conversion systems. The measurements of the IG systems at various speeds and loads are given and show that these systems are capable of good AC and DC voltage regulation.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.380-381
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• 2019

This paper presents a grid voltage-sensorless current control design for an LCL-filtered grid-connected inverter with the purpose of enhancing the reliability and reducing the total cost of system. A disturbance observer based on the gradient steepest descent method is adopted to estimate the grid voltages with high accuracy and light computational burden even under distorted grid conditions. The grid fundamental components are effectively extracted from the estimated gird voltages by means of a least-squares algorithm to facilitate the synchronization process without using the conventional phase-locked loop. Finally, the estimated states of inverter system obtained by a discrete current-type full state observer are utilized in the state feedback current controller to realize a stable voltage-sensorless current control scheme. The effectiveness of the proposed scheme is validated through the simulation results.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.71-73
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• 2008

급변하는 전압 변동 상황에서 전력 제어를 수행하기 위해서 기존의 동기좌표 위상각 검출 제어기의 특성을 보완할 수 있는 방법을 제시하였다. 실질적인 SRF (Synchronous Reference Frame) - PLL(Phase Locked Loop) 시스템에서 계통 전압은 이상적이지 않고 센서 노이즈 등의 저감을 위하여 측정된 전압에 LPF(Low Pass Filter)를 사용하고 있는데 이러한 LPF의 특성을 고려하여 위상각 제어기의 PI게인을 설정하는 방법을 제시하였으며 가변 게인과 LPF 차단주파수 변동방식을 이용하여 전원 전압 사고의 종류에 따라 위상과 전압이 급변하는 경우에 대하여 시뮬레이션과 실험을 통해 제한된 방법으로 동특성이 개선되고 원하는 응답속도로 설계가 가능함을 보였다.

• Journal of Power Electronics
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• v.11 no.5
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• pp.632-638
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• 2011

This paper presents a cascaded coil flux control based on a Current Source Parallel Resonant Push-Pull Inverter (CSPRPI) for Induction Heating (IH) applications. The most important problems associated with current source parallel resonant inverters are start-up problems and the variable response of IH systems under load variations. This paper proposes a simple cascaded control method to increase an IH system's robustness to load variations. The proposed IH has been analyzed in both the steady state and the transient state. Based on this method, the resonant frequency is tracked using Phase Locked Loop (PLL) circuits using a Multiplier Phase Detector (MPD) to achieve ZVS under the transient condition. A laboratory prototype was built with an operating frequency of 57-59 kHz and a rated power of 300 W. Simulation and experimental results verify the validity of the proposed power control method and the PLL dynamics.