• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.227-234
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• 2014

A transceiver for a high-speed inductive-coupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a $10^{-12}$ bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.743-747
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• 2000

The coordinated mechanism of terrestrial vertebrates enables them to maneuver over all of the terrain conditions since they have a distinct ability to adapt to varying conditions. Their locomotions remain infinitely more advanced and elegant than that of present-day existing mechanical walking robots. However, the principles of existing walking robots are based more on technical rather than on biological concepts, yielding unstable locomotion with low speed. In order to apply these advanced biological phenomena to the mechanical design of 4-legged walking robot, modeling methods are introduced and mathematical equations are also introduced.

• Journal of Electrical Engineering and Technology
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• v.5 no.3
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• pp.400-406
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• 2010

This paper deals with parameter tuning of the Power System Stabilizer (PSS) for 612 MVA thermal power plants in the KEPCO system and its validation in a field test. In this paper, the selection of parameters, such as lead-lag time constants for phase compensation and system gain, is optimized using linear and eigenvalue analyses. This is then verified through the time-domain transient stability analysis. In the next step, the performance of PSS is finally verified by the generator's on-line field test. After the field test, measured and simulated data are also compared to prove the effectiveness of the models used in the simulations.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.19.1-19.1
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• 2009

Phase change random access memory (PRAM)은 large sensing signal margin, fast programming speed, low operation voltage, high speed operation, good data retention, high scalability등을 가지는 가장 유망한 차세대 비휘발성 메모리이다. 현재 PRAM용 상변화 재료로는 주로 Ge2Sb2Te5가 사용되고 있지만 reset 전류가 높고 reliability 가 좋지 않아서 새로운 상변화 물질 연구가 필요하다. AgInSbTe (AIST)는 GST와 더불어 열에 의한 가역적 상변화를 하는 소재로 광기록 매체에서는 기록 속도가 빠르고 동작 특성이 우수하다는 특징이 있다. 본 연구에서는 XRD, 비저항측정등을 통해 온도에 따른 AIST의 물성 및 결정화 특성을 분석하고 나노 소자제작을 통해 그 전기적 특성을 평가하였다.

• Proceedings of the KSR Conference
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• 1998.11a
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• pp.161-168
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• 1998

This paper presents an simulation methdology for determining an economical running pattern for a high speed train which minimizes energy consumption under an given trip time margin. The economical running pattern is defined with an economical maximum speed in traction phase, a speed at the end of coasting and a speed at the end of regenerative braking alone in braking phase. An economical run for subways is also described. As a case study, the simulation is carried out fer an economical run of high speed NamSeoul-Pusan line, and the results described. To do this, train performance simulation program is built and extended to be able to find an economical running pattern and then to simulate the defined economical run.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.57-66
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• 2018

It is known that a single-key and a related-key attacks on AES-128 are possible for at most 7 and 8 rounds, respectively. The security of CMAC, a typical block-cipher-based MAC algorithm, has very high possibility of inheriting the security of the underlying block cipher. Since the attacks on the underlying block cipher can be applied directly to the first block of CMAC, the current security margin is not sufficient compared to what the designers of AES claimed. In this paper, we consider HMAC-DM-AES-128 as an alternative to CMAC-AES-128 and analyze its security for reduced rounds of AES-128. For 2-round AES-128, HMAC-DM-AES-128 requires the precomputation phase time complexity of $2^{97}$ AES, the online phase time complexity of $2^{98.68}$ AES and the data complexity of $2^{98}$ blocks. Our work is meaningful in the point that it is the first security analysis of MAC based on hash modes of AES.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.5
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• pp.108-117
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• 1997

To prove the stability and the effectiveness of the robust non-linear friction control suggested and proved analytically in the previous paper, the describing function analysis is introduced. The instability of the Southward's nonlinear friction compensation for a digital position control and the improvement of phase margin of the robust nonlinear friction compensation are verified qualitatively through the describing function analysis. Those controls are applied to a single-axis digital servo driving experimental setup which has inherent stick-slip friction and experimental results confirm the results obtained in and the effectiveness of the robust nonlinear friction compensation for a digital position control.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.51-58
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• 2002

In this paper, a 155/311 Mb/s MUX/DEMUX chip using ECL macrocell away has been developed with a single device. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s(or 311 Mb/s) serial data output, and is to interleave a serial input bit stream of 155 Mb/s(or 311 Mb/s) into the parallel output of 51 Mb/s. The input and output of the device ate TTL compatible at the low-speed end, but 100k ECL compatible at the high-speed end. The device has been fabricated with Motorola ETL3200 macrocell away The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 220ps at the high-speed end.