• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.95-98
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• 2012

본 논문은 40 MHz에서 280 MHz 동작 주파수에서 32-phase clock을 출력하는 multiphase delay-locked loop (DLL)을 제안한다. 제안된 multiphase DLL은 고해상도의 1-bit delay를 위하여 matrix구조의 delay line을 사용한다. Delay line의 선형성을 향상시키기 위하여 matrix 입력단의 비선형성을 보정할 수 있는 기법이 사용된다. 설계된 multiphase DLL은 1.2 V supply를 이용하는 0.11-${\mu}m$ CMOS 공정에서 제작되었다. 125 MHz 동작 주파수에서 multiphase DLL의 DNL은 +0.51/-0.12 LSB 이하로 측정되었으며, input clock의 jitter가 peak-to-peak jitter가 12.9ps일 때 출력clock의 peak-to-peak jitter는 30 ps이다. 면적과 전력 소모는 각각 $480{\times}550{\mu}m^2$과 1.2 V 공급전압에서 9.6 mW이다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2004년도 SMICS 2004 International Symposium on Maritime and Communication Sciences
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Journal of electromagnetic engineering and science
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• 제3권1호
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• pp.62-66
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• 2003

Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

• 한국군사과학기술학회지
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• 제20권3호
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• pp.413-420
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• 2017

We investigate the performance of a true time delay(TTD) phase shifter to reduce the beam squint caused by frequency changes of a phased array antenna in wideband communication systems. To design a high gain phased array antenna, we need a long TTD, which causes high RF loss, low resolution and large dimension of TTD phase shifters. To overcome the problems, we propose a schematic of dual TTD phase shifters, which consists of short time delay(STD) in radio frequency(RF) part and long time delay(LTD) in intermediate frequency(IF) part. Our analysis results show that the proposed scheme reduces the required bits and delay time in RF band of the TTD compared to the conventional single TTD scheme.

• 한국정보통신학회논문지
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• 제9권4호
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• pp.861-864
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• 2005

광위상변조기를 이용하여 OCT용 초고속 광지연단을 설계하고 수치해석을 수행하였다. 수치해석은 electro-optic 위상 변조기에 1310nm, 10ps의 펄스폭을 갖는 레이저 광원을 적용하여 수행하였다. 수치해석결과로 500MHz의 변조 주파수일때 19ps의 시간 지연을 얻었으며, 이는 기존의 기계적 검출 방식(수십kHz)의 OCT장치에 비해 1000배이상 빠른 검출이 가능할 것으로 예상된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3184-3186
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• 1999

In this paper, a new structure of fully differential delay cell VCO using quadrature phase for low phase noise and high speed operation is suggested. It is realized by inserting voltage clamp circuit into input pairs of delay cells that include three-control current source having high output impedance. In this reason. this newly designed delay cell for VCO has the low power supply sensitivity so that the phase noise can be reduced. The whole characteristics of VCO were simulated by using HSPICE and SABER. Simulation results show that the phase noise of new VCO is quite small compared with conventional fully differential delay cell VCO and ring oscillator type VCO. It is also very beneficial to low power supply design because of wide tuning range.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.63-64
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• 2011

The inevitable calculation time delay of digital controller especially degrades the voltage control performance of three-phase UPS systems. This paper proposes time delay compensators based on the Smith-predictor for both voltage and current controllers of three-level NPC inverters. The PSIM-based simulation results show that the proposed controller with delay compensator gives improved voltage control performance with respect to time delay.

• 전기학회논문지
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• 제58권1호
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• pp.187-192
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• 2009

This paper presents a method for designing a robust controller that alleviates disturbance effects and compensates performance degradation owing to the time-delay. Disturbance observer(DOB) approach as a tool of robust control has been widely employed in industry. However, since the Pade approximation of time-delay makes the plant non-minimum phase, the classical DOB cannot be applied directly to the system with time-delay. By using a new DOB structure for non-minimum phase systems together with the Smith Predictor, we propose a new controller for reducing the both effects of disturbance and time-delay. Moreover, the closed-loop system can be made robust against uncertain time-delay with the help of a Pill controller tuning method that is based on a second-order plus dead time modeling technique.

• Current Optics and Photonics
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• 제8권1호
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• pp.56-64
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• 2024

In response to the current situation where general methods cannot effectively compensate for the phase delay of ordinary optical mixers, a multi-layer spatial beam-splitting optical mixer is designed using total reflection triangular prisms and polarization beam splittings. The phase delay is generated by the wave plate, and the mixer can use the existing parallel plates in the structure to individually compensate for the phase of the four output beams. A mixer model is established based on the structure, and the influence of the position and orientation of the optical components on the phase delay is analyzed. The feasibility of the phase compensation method is simulated and analyzed. The results show that the mixer can effectively compensate for the four outputs of the optical mixer over a wide range. The mixer has a compact structure, good performance, and significant advantages in phase error control, production, and tuning, making it suitable for free-space coherent optical communication systems.

• 대한전자공학회논문지SD
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• 제47권6호
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• pp.51-56
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• 2010

본 논문에서는 전압제어위상지연단(Voltage Controlled Delay Line : VCDL)을 이용하여 기존의 위상고정루프와 다른 형태의 위상 지연고정루프(Phase Delay Locked Loop)를 제안 하였다. 이 구조는 기존의 위상고정루프의 2차 또는 3차 루프필터(Loop Filter)를 단하나의 커패시터로 구현하여 넓은 면적을 차지하던 루프필터의 면적을 크게 줄여 전체 칩을 $255{\mu}m$ $\times$ $935.5{\mu}m$ 크기로 집적하였다. 제안된 회로는 1.8V $0.18{\mu}m$ CMOS 공정의 파라미터를 이용하여 HSPICE로 시뮬레이션을 수행하고 회로의 동작을 검증하였다.