• International Journal of Advanced Culture Technology
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• v.7 no.1
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• pp.225-230
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• 2019

In order to improve performance for the size of the rat-race ring coupler, the CCL is used for the realization as the delay line. As realizing lower coupling coefficient, the ratio of the size-reduction for the CCL is enhanced. The CCL is alternated with ${\lambda}_g/4$ of the rat-race ring, and optimized two CCLs are inserted for the size-reduction. the coupling coefficient is 0.2, and electrical lengths of each CCL are $28.2^{\circ}$ and $21.7^{\circ}$. Designed rat-race ring using the CCL has the size of $18.76{\times}20.45mm^2$ and the size-reduction ratio of fabricated rat-race ring using the CCL has 76.8%. Also, fabricated rat-race ring is measured the insertion loss of 3.20dB at the center frequency of 2.45GHz and the 20dB bandwidth is 24.04%. Differenced magnitude and phase between threw port and coupled port are measured 0.1dB and $177.4^{\circ}$, respectively. These performances are almost same compared with the conventional rat-race ring. Suggested application of the CCL can be used various devices and circuits for the size-reduction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.268-271
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• 2001

This paper presents observer-based on-line overload monitoring scheme for a PMSM(Permanent Magnet Synchronous Motor) drive system. Proposed scheme is to monitor overload status of motor drive system at remote place. The drive system is previously installed on main system and has no communication function. Proposed scheme consists of intelligent sensing head and monitoring part. Intelligent sensing head acquire motor 3-Phase currents and transmit data to monitoring part over serial communication interface. Monitoring part estimates motor speed using state observer. By comparing estimated speed with reference speed, we can detect motor fault. In this scheme observed information must coded and transmitted over a digital communication channel with finite capacity. We consider communication constraint as time delay and we design discrete-time observer. The proposed scheme is tested on the actual drive system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.2
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• pp.67-73
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• 2015

Distance relay is widely used for the protection of long transmission line. Most of distance relay used to calculate line impedance by measuring voltage and current using DFT. So if there is a computation error due to the influence of phasor by DC offset component, due to excessive vibration by measuring line impedance, overreach or underreach can be occurs, and then abnormal and non-operation of distance relay can be issue. It is very important to implement the robust distance relaying that is not affected by DC offset component. This paper describes an enhanced distance relaying based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any prior information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced distance relay uses fault current as well as residual current. The behavior of the proposed distance relaying using off-line simulation has been verified using data about several fault conditions generated by the ATP simulation software.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.102-108
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• 1991

Utilizing self-phase modulation effects of a dispersion-shifted fiber and delay-line characteristics of two gratings, mode-locked 80 ps pulses at 1.319${\mu}{\textrm}{m}$ wavelength from a Nd: YAG laser are compressed down to 2.1 ps. These pulses are further compressed down to 340 fs using higher order soliton effects in a common single mode fiber.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.3
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• pp.112-119
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• 1982

An experimental 2400bps modem emlpoying 4-phase DPSK in compliance with the CCITT recommendation V.26 is developed. Integrated circuits are used throughtout the circuit implementation, including active filters and a semiconductor delay line. A new timing recovery scheme is proposed and adopted successfully. The error rate perfromance is found to be in fair agreement with the theoretical prediction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.14-18
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• 2006

Optical interferometer is used for various optical measurement fields in optical metrology and biomedical measurements. In an optical interferometer, optical delay line has to change the optical path length of a reference arm to match with that of a sample in and it's speed was limited by reference arm movement speed. In this paper, we proposed an all-fibered RSODRapid Scanning-speed Optical Delay) without any mechanical movement, and we applied this system to optical interferometer. Experimental setup is consist of pulse laser source (center wavelength 1304nm, pulse width 30ps, repetition rate 10GHz), two phase modulators and dispersive shifted fiber. As experimental results, we obtain the maximum time delay of 11ps at 10MHz repetition rate, and it is easily tuneable the time delay by modulation frequency and modulation voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.4
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• pp.401-412
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• 2003

In this paper, a broadband phase shifter structure using a new switched network was proposed. A new reference network is composed of coupled lines and 45$^{\circ}$open and short stubs, which are shunted at the edge points of a main line, respectively, A delay network is composed of only a standard transmission line. It is possible to design a broadband 180$^{\circ}$phase shifter that phase dispersive characteristics by an impedance ratio R of coupled lines and greater phase dispersive characteristics by characteristic impedances Zm, Zs of a main line and stubs are used together. By considering a structure symmetry, the even and odd mode analysis was performed to obtain theoretical S-parameters of the proposed phase shifter. Also, through computer simulation on the basis of derived equations, design graphs were presented to optimally design a 180$^{\circ}$broadband phase shifter. Design graphs provide the values of characteristic impedances Zm, Zs, and I/O match and phase bandwidths. To verify electrical performances of the broadband phase shifter proposed in this paper, low different 180$^{\circ}$phase shifters, operated at the center frequency 3 GHz were designed and fabricated using design graphs, and were experimented. One of them was designed as a standard Schiffman structure to compare with electrical performances. Measured results of each phase shifter to satisfy simultaneously design conditions of I/O match （VSWR=1.15:1) and maximum phase deviation $({\varepsilon}_{{\Delta}{\phi}}＝{\pm}2^{\circ})$ were well in agreement with corresponding simulation results over impedance match and phase error bandwidths, and showed broadband characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.213-219
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• 2007

In this paper, A novel structure of frequency doubler using Phase Delay line and $90^{\circ}$ Hybrid coupler at harmonic output have been designed and implemented to improve suppression. Proposed structure of frequency doubler improve output. coupling and fundamental suppression. Active frequency doubler with band from $2.13{\sim}2.15GHz\;to\;4.26{\sim}4.3GHz$ was designed and fabricated with 10dBm input power, 0.79dB conversion gain and -55.54dBc suppression at fundamental frequency, -44.76dBc suppression at third harmonic frequency 6.42GHz and -39.18dBc suppression at fourth harmonic frequency 8.56GHz.