• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.886-888
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• 1993

Recently current mode control is widely adopted in switching power converter because of inherent stablity and ability of parallel operating. There are several ways in current mode control. One of them, peak current control is chiefly employed. Peak current mode control converter usually senses and controls peak inductor current. But there is peak-to-average current errors. Therefore peak current control needs compensation ramp correcting the errors. Average current mode control eliminates these problems, and is constructed by simple structures. This paper will describe the behavior of a simple average current mode boost converter and introduce the design techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.810-817
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• 2014

An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ns, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 83%.

• 전력전자학회논문지
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• 제3권4호
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• pp.338-345
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• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannons sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannons sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practial smapler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1970-1979
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• 2017

Ultra Lift Luo Converter (ULC) gained considerable research interest in recent years. The stability analysis of voltage mode and peak current mode controlled ULC in continuous conduction mode is analyzed in this paper. The Eigen value theory is used for the stability analysis of voltage mode controlled ULC. Then to characterize the dynamics of inner current loop, the expressions of closed loop transfer function and loop gain are determined. An algorithm has been developed to analyze the stability of the peak current mode controlled ULC. The theoretical results are correlated with the simulation results obtained using PSIM 9.1(SMARTCTRL 1.0) software. Finally it is proposed to fabricate a prototype and validate the performance by suitable experimental setup.

• 전력전자학회논문지
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• 제24권2호
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• pp.134-137
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• 2019

A wide-bandwidth current controller is required for fast charging/discharging of super capacitor applications. Peak current mode is generally used to accomplish fast charging/discharging because this mode has fast response characteristics. However, the peak current mode control must have a slope compensation function to restrain sub-harmonics oscillation. The slope must be changed accordingly if the controlled output voltage is varied. However, changing the slope for every changed output voltage is not easy. The other solution, selecting the slope as the maximum value, causes a slow response problem to occur. Therefore, we propose a hybrid mode controller that uses a peak current and a newly specified valley current. Through the proposed hybrid mode control, the sub-harmonic oscillation does not occur when the duty is larger than 0.5 because of the fast response.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.275-278
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• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannon's sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannon's sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practical sampler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Journal of Power Electronics
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• 제12권5호
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• pp.715-722
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• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• 전기전자학회논문지
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• 제17권1호
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• pp.77-82
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• 2013

본 논문에서는 인덕터의 흐르는 전류를 감지하여 출력 전압을 일정하게 유지시키는 Peak Current-mode 방식의 DC-DC Buck Converter를 제안하고, 소신호 모델링에 기초하여 Power Stage 설계 방법과 시스템의 안정도를 설계하는 방법을 제안한다. 또한, dc-dc 컨버터의 신뢰성과 성능을 향상시키기 위해 보호회로를 추가하였다. 그리고 정전기 방지를 위하여 ESD 보호회로를 제안하였다. 제안된 보호회로는 게이트-기판 바이어싱 기술을 이용하여 낮은 트리거 전압을 구현하였다. 시뮬레이션 결과는 일반적인 ggNMOS의 트리거 전압(8.2V) 에 비해 고안된 소자의 트리거 전압은 4.1V 으로 더 낮은 트리거 전압 특성을 나타냈다. 본 논문에서 제안하는 회로의 시뮬레이션은 0.35um BCB 공정 파라미터를 이용하였고, Mathworks 사의 Mathlab과 Synopsys 사의 HSPICE 프로그램을 사용하여 검증하였다.

• 전기학회논문지
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• 제58권2호
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• pp.301-307
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• 2009

In the paralleled converter module with peak current mode control, current imbalance appears when the voltage controllers with integral control of converter module are not exactly identical. In this paper, the voltage controller is designed to equal the current command of each converter module using the current command bus. The current balance controller is also proposed to balance the average currents of converter modules with imbalaced inductance. It is designed to have good transient response. Proposed method is implemented with the paralleled 2-module and 4-module boost converters with imbalanced inductance. Experimental results verify the performance of current share during both steady and transient states of converter.