• Title/Summary/Keyword: Peak current control

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A SiC MOSFET Based High Efficiency Interleaved Boost Converter for More Electric Aircraft

  • Zaman, Haider;Zheng, Xiancheng;Yang, Mengxin;Ali, Husan;Wu, Xiaohua
    • Journal of Power Electronics
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    • v.18 no.1
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    • pp.23-33
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    • 2018
  • Silicon Carbide (SiC) MOSFET belongs to the family of wide-band gap devices with inherit property of low switching and conduction losses. The stable operation of SiC MOSFET at higher operating temperatures has invoked the interest of researchers in terms of its application to high power density (HPD) power converters. This paper presents a performance study of SiC MOSFET based two-phase interleaved boost converter (IBC) for regulation of avionics bus voltage in more electric aircraft (MEA). A 450W HPD, IBC has been developed for study, which delivers 28V output voltage when supplied by 24V battery. A gate driver design for SiC MOSFET is presented which ensures the operation of converter at 250kHz switching frequency, reduces the miller current and gate signal ringing. The peak current mode control (PCMC) has been employed for load voltage regulation. The efficiency of SiC MOSFET based IBC converter is compared against Si counterpart. Experimentally obtained efficiency results are presented to show that SiC MOSFET is the device of choice under a heavy load and high switching frequency operation.

Single-Phase Power Factor Correction(PFC) Converter Using the Variable gain (가변이득을 가지는 디지털제어 단상 역률보상회로)

  • Baek, J.W.;Shin, B.C.;Jeong, C.Y.;Lee, Y.W.;Yoo, D.W.;Kim, H.G.
    • Proceedings of the KIEE Conference
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    • 2001.04a
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    • pp.240-243
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    • 2001
  • This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

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Dynamic Characteristics Control of a Step-down Chopper Using Load current Feed-forward Compensator (부하전류 전향보상기를 이용한 강압쵸퍼의 동특성 제어)

  • Chung, Chun-Byung;Chun, Ji-Yong;Jeon, Kee-Young;Han, Kyung-Hee
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2008.05a
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    • pp.66-69
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    • 2008
  • In this paper, The author present a load current feed-forward compensator by method that improve voltage controller of Step-down Chopper to get stable output voltage to sudden change of load current. To confirm the characteristicsof a presented load current feed -forward compensator compared each transfer function of whole system that load current feed-forward compensator is added with transfer function of whole system that existent voltage controller is included using Mason gains formula in Root locus and Bode diagram. As a result the pole of system is improved, extreme point of the wave and system improves, and size of peak value and phase margin of break frequency in resonance frequency confirmed that is good. Therefore, presented control technique could confirm that reduce influence by perturbation and improves stationary state and dynamic characteristics in output of Step-down Chopper.

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A High-efficiency Method to Suppress Transformer Core Imbalance in Digitally Controlled Phase-shifted Full-bridge Converter

  • Yu, Juzheng;Qian, Qinsong;Sun, Weifeng;Zhang, Taizhi;Lu, Shengli
    • Journal of Power Electronics
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    • v.16 no.3
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    • pp.823-831
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    • 2016
  • A high-efficiency method is proposed to suppress magnetic core imbalance in phase-shifted full-bridge (PSFB) converters. Compared with conventional solutions, such as controlling peak current mode (PCM) or adding DC blocking capacitance, the proposed method has several advantages, such as lower power loss and smaller size, because the additional current sensor or blocking capacitor is removed. A time domain model of the secondary side is built to analyze the relationship between transformer core imbalance and cathode voltage of secondary side rectifiers. An approximate control algorithm is designed to achieve asymmetric phase control, which reduces the effects of imbalance. A 60 V/15 A prototype is built to verify the proposed method. Experimental results show that the numerical difference of primary side peak currents between two adjacent cycles is suppressed from 2 A to approximately 0 A. Meanwhile, compared with the PCM solution, the efficiency of the PSFB converter is slightly improved from 93% to 93.2%.

A numerical study on the feasibility evaluation of a hybrid type superconducting fault current limiter applying thyristors

  • Nam, Seokho;Lee, Woo Seung;Lee, Jiho;Hwang, Young Jin;Ko, Tae Kuk
    • Progress in Superconductivity and Cryogenics
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    • v.15 no.4
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    • pp.26-29
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    • 2013
  • Smart fault current controller (SFCC) proposed in our previous work consists of a power converter, a high temperature superconducting (HTS) DC reactor, thyristors, and a control unit [1]. SFCC can limit and control the current by adjusting firing angles of thyristors when a fault occurs. SFCC has complex structure because the HTS DC reactor generates the loss under AC. To use the DC reactor under AC, rectifier that consists of four thyristors is needed and it increases internal resistance of SFCC. For this reason, authors propose a hybrid type superconducting fault current limiter (SFCL). The hybrid type SFCL proposed in this paper consists of a non-inductive superconducting coil and two thyristors. To verify the feasibility of the proposed hybrid type SFCL, simulations about the interaction of the superconducting coil and thyristors are conducted when fault current flows in the superconducting coil. Authors expect that the hybrid type SFCL can control the magnitude of the fault current by adjusting the firing angles of thyristors after the superconducting coil limits the fault current at first peak.

Effects of Vth adjustment ion implantation on Switching Characteristics of MCT(MOS Controlled Thyristor) (문턱전압 조절 이온주입에 따른 MCT (MOS Controlled Thyristor)의 스위칭 특성 연구)

  • Park, Kun-Sik;Cho, Doohyung;Won, Jong-Il;Kwak, Changsub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.69-76
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    • 2016
  • Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

PWM Converter Control considering time varying source voltage (Time Varying 전원 전압을 고려한 PWM 컨버터 제어)

  • 주인원;임선경;남광희
    • Proceedings of the KIPE Conference
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    • 1999.07a
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    • pp.692-695
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    • 1999
  • A new control scheme is proposed suitable for the three phase PWM converter having abrupt load variation such as a crane. In the converter used in a crane, the peak value of source voltage varies instantaneously due to the abrupt load variations. Such a voltage variation degrades the performance of DC-link control of PWM converter. To overcome this problem, load variations should be detected and compensated properly. We propose a new method for detecting and compensating the load variations without the additional hardware. With the proposed scheme, load variations are detected by estimating the current of DC-link capacitor. The estimated current information is feedbacked to a current controller to improve the performance. Additionally, the variation of source voltage is compensated using feedforward controller. The performance of the proposed scheme has been verified through simulations.

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Slope Compensation Design of Buck AC/DC LED Driver Based on Discrete-Time Domain Analysis (이산 시간 영역 해석에 기반한 벅 AC/DC LED 구동기의 슬로프 보상 설계)

  • Kim, Marn-Go
    • The Transactions of the Korean Institute of Power Electronics
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    • v.24 no.3
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    • pp.207-214
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    • 2019
  • In this study, discrete-time domain analysis is proposed to investigate the input current of a buck AC/DC light-emitting diode (LED) driver. The buck power factor correction converter can operate in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). Two discontinuous and two continuous conduction operating modes are possible depending on which event terminates the conduction of the main switch in a switching cycle. All four operating modes are considered in the discrete-time domain analysis. The peak current-mode control with slope compensation is used to design a low-cost AC/DC LED driver. A slope compensation design of the buck AC/DC LED driver is described on the basis of a discrete-time domain analysis. Experimental results are presented to confirm the usefulness of the proposed analysis.

Design and Implementation of Photovoltaic Power Conditioning System using a Current-based Maximum Power Point Tracking

  • Lee, Sang-Hoey;Kim, Jae-Eon;Cha, Han-Ju
    • Journal of Electrical Engineering and Technology
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    • v.5 no.4
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    • pp.606-613
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    • 2010
  • This paper proposes a novel current-based maximum power point tracking (CMPPT) method for a single-phase photovoltaic power conditioning system (PV PCS) by using a modified incremental conductance method. The CMPPT method simplifies the entire control structure of the power conditioning system and uses an inherent current source characteristic of solar cell arrays. Therefore, it exhibits robust and fast response under a rapidly changing environmental condition. Digital phase locked loop technique using an all-pass filter is also introduced to detect the phase of grid voltage, as well as the peak voltage. Controllers of dc/dc boost converter, dc-link voltage, and dc/ac inverter are designed for coordinated operation. Furthermore, a current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. A 3 kW prototype PV PCS is built, and its experimental results are given to verify the effectiveness of the proposed control schemes.

An Automatic Power Control Circuit suitable for High Speed Burst-mode optical transmitters (고속 버스트 모드 광 송신기에 적합한 자동 전력 제어 회로)

  • Ki, Hyeon-Cheol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.98-104
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    • 2006
  • The conventional burst-mode APC(Automatic Power Control) circuit had an effective structure that was suitable for a low power consumption and a monolithic chip. However, as data rate was increased, it caused errors due to the effect of the zero density. In this paper, we invented a new structured peak-comparator which could compensate the unbalance of the injected currents using double gated MOS and MOS diode. And we proposed a new burst-mode APC adopting it. The new peak-comparator in the proposed APC was very robust to zero density variations maintaining the correct decision point of the current comparison at high data rate. It was also suitable for a low power consumption and a monolithic chip due to lack of large capacitors.