• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.993-997
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• 1997

The continuous chip depresses the accuracy of workpieces and promotes the wear of machine tools and hunts operators. So chip control os a major problem in turning process. In this paper, a method of chip identification is develope by pyrometer. The identifier is applied in real-time control of chip pattern with adjusting feedrate.

• 대한전자공학회논문지
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• 제18권4호
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• pp.34-42
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• 1981

PMOS집적기술을 이용하여 512-Bit mask programmable ROM을 설계하고 제작하였다. ROM의 내용은 제작공정에서 gate pattern으로 기억시켰으며 chip의 출력을 512(32×16)개의 점의 행렬로써 오실로스코프에 나타내어 확인하였다. 제작된 chip은 -6V와 - l2V의 범위에서 정상적으로 동작하였다 소모전력과 전달지연시간은 -6V에서 각각 3mW와 13μsec였다. -12V에서는 소모전력이 27mW로 증가하였으며 전달지연시간은 3μsec로 감소하였다. Chip의 출력은 TTL gate의 인력을 직접 구동시킬 수 있었으며 chip select에 의하여 출력을 disable 시켰을 때는 높은 임피던스 상태를 유지하였다.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.201-206
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• 2007

본 논문에서는 NoC(Network-on Chip) 구조로 구현된 core-based 시스템에 대한 효율적인 저전력 테스트 방법을 제안한다 NoC의 라우터 채널로 전송되는 테스트 데이터의 전력소모를 줄이기 위해서 스캔 벡터들을 채널 폭만큼의 길이를 갖는 flit으로 분할하고 nit간 천이율(switching rate)이 최소화 되도록 don't care 입력을 할당하였다. ISCAS 89 벤치마크에 대하여 실험을 한 결과, 제안된 방법은 약 35%의 전력 감소를 나타내었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권8호
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• pp.443-446
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• 2004

In this paper, a multi-band ceramic chip antenna for WLAN(Wireless LAN) applications is designed. The design target is to obtain 0 dBi of coverage gain with omni directional radiation pattern. The antenna is fabricated using Low Temperature Co-fired Ceramic(LTCC) technology. The size of the chip antenna is $2.2{\times}9.65{\times}1.02$mm. The measured antenna gain is 1 dBi at 2.44 GHz and 0.5 dBi at 5.5 GHz. The omni directional radiation pattern for the two operating bands is obtained. The measured bandwidth(S11=-10 dB) are 90 MHz at 2.44 GHz and 1280 MHz at 5.5 GHz respectively

• 한국정밀공학회지
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• 제13권7호
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• pp.59-65
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• 1996

A major problem in automation of turning operations is the difficulty in obtaining a sufficient and reliable chip control. Therefore it becomes desirable to find a method which can detect the chip form. Newly born chips in usual metal cutting radiate infrared rays. When such chips run out of cutting point quickly, the radiated energy from the zone around the tool is low compared with that of the case when long tangled chips are staying around the tool. The difference in chip pattern can be detected from the output of pyrometer. But, strictly speaking, only the output of pyrometer does not identify the chip form because that is the removal of chip. Therefore, in this paper, a method of the identification of chip form using output of pyrometer and fuzzy inference is developed.

• Journal of the Korean Wood Science and Technology
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• 제16권4호
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• pp.54-60
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• 1988

Machinabilities means inherent properties of pinus densiflora at Chunyang district to be CNC machined easily or not, and processing abilities of the tool and machine together. This explanation signifies that machinabilities have two phases of signification, depended on considering and stress either materials or tools preferentially. This paper discuss machinabilities, the following items are usually employed as the indices of stress distribution at the cutting tool rake face. The stress distributions on the chip - tool contact surface at the early stage of the chip forming and under the stage of fringe pattern in wood cutting were analyzed the photoelastic method. The tool used in the present experiment was the special cutting tool H.S.S. one made in laboratory. And isochromatic fringe pattern and isolinic line of work piece by chip-behavior during the cutting operation were photographed with the feed camera continuously. The effects on the stress, distribution on the rake face of the epoxy tool and the strain distribution in the work piece of wood plate by chip behavior are cleared in pre cent experiment.

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.53-57
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• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.553-556
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• 1988

Recognition of IC chip pattern requires extraction of features, which have the information of vertex position and orientation. Edges are extracted and straightening algorithm is applied to the edges, so that lines are obtained. With these extracted data, the coordinate and orientation of all vertices are extracted and vertex-form matching is applied to the locally overlapped area of neighborhood frames to have global coordinate of IC chip.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권12호
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• pp.589-595
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• 2004

The ESD protection characteristic of chip varistors on a circuit board can not be analyzed by using a conventional circuit simulator due to its microwave characteristic. Thus, by employing Agilent's microwave circuit simulator ADS, we showed that the ESD Protection characteristic or chip varistors can be investigated. order to got more precise simulation results, a chip varistor model was extracted from the electrical characteristic of a TDK's chip varistor and the distributed circuit based pattern was designed as the ESD propagation path. The simulation results showed that the ESD protection characteristic of a chip varistors can be improved drastically by reducing the ESD propagation path.

• 전자공학회논문지A
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• 제33A권5호
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• pp.203-211
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• 1996

This paper describes CAD tools for the construction of image database in IC chip analysis CAD system. For IC chip analysis by high-resolution microscopy, the image database is essential to manage more than several thousand images. But manual database construction is error-prone and time-consuming. In order to solve this problem, we develop a set of CAD toos that include image grabber to capture chip images, image editor to make the whole chip image database from the grabbed images, and image divider to reconstruct the database that consists of evenly overlapped images for efficient region search. we also develop an interactive pattern matching method for user-friendly image editing, and a heuristic region search method for fast image division. The tools are developed with a high-performance graphic hardware with JPEG image comparession chip to process the huge color image data. The tools are under the field test and experimental resutls show that the database construction time can be redcued in 1/3 compared to manual database construction.