• Title/Summary/Keyword: Path-based Computation

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Computation of stress-deformation of deep beam with openings using finite element method

  • Senthil, K.;Gupta, A.;Singh, S.P.
    • Advances in concrete construction
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    • v.6 no.3
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    • pp.245-268
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    • 2018
  • The numerical investigations have been carried out on deep beam with opening subjected to static monotonic loading to demonstrate the accuracy and effectiveness of the finite element based numerical models. The simulations were carried out through finite element program ABAQUS/CAE and the results thus obtained were validated with the experiments available in literature. Six simply supported beams were modelled with two square openings of 200 and 250 mm sides considered as opening at centre, top and bottom of the beam. In order to define the material behaviour of concrete and reinforcing steel bar the Concrete Damaged Plasticity model and Johnson-Cook material parameters available in literature were employed. The numerical results were compared with the experiments in terms of ultimate failure load, displacement and von-Mises stresses. In addition to that, seventeen beams were simulated under static loading for studying the effect of opening location, size and shape of the opening and depth, span and shear span to depth ratio of the deep beam. In general, the numerical results accurately predicted the pattern of deformation and displacement and found in good agreement with the experiments. It was concluded that the structural response of deep beam was primarily dependent on the degree of interruption of the natural load path. An increase in opening size from 200 to 250 mm size resulted in an average shear strength reduction of 35%. The deep beams having circular openings undergo lesser deflection and thus they are preferable than square openings. An increase in depth from 500 mm to 550 mm resulted in 78% reduced deflection.

Design of Hash Processor for SHA-1, HAS-160, and Pseudo-Random Number Generator (SHA-1과 HAS-160과 의사 난수 발생기를 구현한 해쉬 프로세서 설계)

  • Jeon, Shin-Woo;Kim, Nam-Young;Jeong, Yong-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.1C
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    • pp.112-121
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    • 2002
  • In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

A VLSI Architecture of Systolic Array for FET Computation (고속 퓨리어 변환 연산용 VLSI 시스토릭 어레이 아키텍춰)

  • 신경욱;최병윤;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.9
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    • pp.1115-1124
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    • 1988
  • A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

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Design of AES Cryptographic Processor with Modular Round Key Generator (모듈화된 라운드 키 생성회로를 갖는 AES 암호 프로세서의 설계)

  • 최병윤;박영수;전성익
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.5
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    • pp.15-25
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    • 2002
  • In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

unifying solution method for logical topology design on wavelength routed optical networks (WDM의 논리망 구성과 파장할당 그리고 트래픽 라우팅을 위한 개선된 통합 해법)

  • 홍성필
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.9A
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    • pp.1452-1460
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    • 2000
  • A series of papers in recent literature on logical topology design for wavelength routed optical networks have proposed mathematical models and solution methods unifying logical topology design wavelength assignment and traffic routing. The most recent one is by Krishnaswamy and Sivarajan which is more unifying and complete than the previous models. Especially the mathematical formulation is an integer linear program and hence regarded in readiness for an efficient solution method compared to the previous nonlinear programming models. The solution method in [7] is however elementary one relying on the rounding of linear program relaxation. When the rounding happens to be successful it tends to produce near-optimal solutions. In general there is no such guarantee so that the obtained solution may not satisfy the essential constraints such as logical -path hop-count and even wavelength number constraints. Also the computational efforts for linear program relaxation seems to be too excessive. In this paper we propose an improved and unifying solution method based on the same to be too excessive. In this paper we propose an improved and unifying solution method based on the same model. First its computation is considerably smaller. Second it guarantees the solution satisfies all the constraints. Finally applied the same instances the quality of solution is fairly competitive to the previous near optimal solution.

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Compatibility of DOAS and Conventional Point Monitoring System Through an Evaluation of Bias Structures Using Long-term Measurement Data in Seoul (장기관측자료를 이용한 DOAS와 점측정 분석시스템의 바이어스 구조에 대한 평가)

  • 김기현;김민영
    • Journal of Korean Society for Atmospheric Environment
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    • v.17 no.5
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    • pp.395-405
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    • 2001
  • To make an assessment of the compatibility between DOAS and conventional point monitoring system (MCSAM-2: MS2), we investigated the concentrations of three criteria pollutants which include S $O_2$, N $O_2$, and $O_3$from a national monitoring station in Seoul during the periods of June 1999~August 2000. The average concentration values for the whole study period derived from hourly concentration data sets of those three species indicated that the mean differences between the two methods can be approximated as 18%. When the bias structure of two systems was evaluated through the computation of percent difference(PD) between the two such as ( $C_{DOAS}$- $C_{conventional}$ $C_{DOAS}$*100, differences between the two systems appeared to be quite systematic among different compounds. While the mode of bias peaked at 0~20% or 20~40% in terms of PD values, the cause of such positive bias mainly arised from generally enhanced concentration values of DOAS system. The structure of bias among different species was further assessed through linear regression analysis. Results of the analysis indicated that the dominant portions of differences observed from two monitoring systems can be accounted for by the systematic differences in their spanning and zeroing systems. S $O_2$(MS2)=0.6385 S $O_2$(DOAS)+2.0985($r^2$=0.7894) N $O_2$(MS2)=0.6548 N $O_2$(DOAS)+7.437($r^2$=0.7687) $O_3$(MS2)=1.0359 $O_3$(DOAS)-7.7885($r^2$=0.7944) The findings of slope values at around 0.64~0.65 from two species suggest that DOAS should respond more sensitively in upper bound concentration range. The offset values apart from zero indicate that more deliberate comparison needs to be made between these monitoring systems. However, based on the existence of strong correlations from at least 8,000 data points for each species of comparison, we were able to conclude that the compatibility of two monitoring systems is highly significant. With the improvement of calibration techniques for the DOAS system. its applicability for routine monitoring of airborne pollutant species is expected to be quite extendable.

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Shape Design Optimization of Crack Propagation Problems Using Meshfree Methods (무요소법을 이용한 균열진전 문제의 형상 최적설계)

  • Kim, Jae-Hyun;Ha, Seung-Hyun;Cho, Seonho
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.27 no.5
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    • pp.337-343
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    • 2014
  • This paper presents a continuum-based shape design sensitivity analysis(DSA) method for crack propagation problems using a reproducing kernel method(RKM), which facilitates the remeshing problem required for finite element analysis(FEA) and provides the higher order shape functions by increasing the continuity of the kernel functions. A linear elasticity is considered to obtain the required stress field around the crack tip for the evaluation of J-integral. The sensitivity of displacement field and stress intensity factor(SIF) with respect to shape design variables are derived using a material derivative approach. For efficient computation of design sensitivity, an adjoint variable method is employed tather than the direct differentiation method. Through numerical examples, The mesh-free and the DSA methods show excellent agreement with finite difference results. The DSA results are further extended to a shape optimization of crack propagation problems to control the propagation path.

LLR-based Cooperative ARQ Protocol in Rayleigh Fading Channel (레일리 페이딩 채널에서 LLR 기반의 협력 ARQ 프로토콜)

  • Choi, Dae-Kyu;Kong, Hyung-Yun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.4
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    • pp.31-37
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    • 2008
  • Conventional cooperative communications can attain gain of spatial diversity and path loss reduction because destination node independently received same signal from source node and relay node located between source node and destination node. However, these techniques bring about decreased spectral efficiency with relay node and increased complexity of receiver by using maximal ratio combining (MRC). This paper has proposed cooperative ARQ protocol that can improve the above problems and can get the better performance. This method can increase the spectral efficiency than conventional cooperative communication because if the received signal from source node is satisfied by the destination preferentially, the destination transmits ACK message to both relay node and source node and then recovers the received signal. In addition, if ARQ message indicates NACK relay node operates selective retransmission and we can increase reliability of system compared with that of general ARQ protocol in which source node retransmits data. In the proposed protocol, the selective retransmission and ARQ message are to be determined by comparing log-likelihood ratio (LLR) computation of received signal from source node with predetermined threshold values. Therefore, this protocol don't waste redundant bandwidth with CRC code and can reduce complexity of receiver without MRC. We verified spectral efficiency and BER performance for the proposed protocol through Monte-Carlo simulation over Rayleigh fading plus AWGN.