• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3A
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• pp.179-184
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• 2003

In this paper, an asymmetric topology of MMIC SPDT switch was proposed to increase the isolation in the receiving path and decrease the insertion loss with higher P1dB in the transmitting path for the ISM band. This SPDT switch was implemented with 0.5㎛ GaAs MESFETs processed by ETRI for the IDEC MPW project. For the receiving path the measured insertion losses were 1.518dB at 3GHz and 1.777dB at 5.75GHz and the isolations were 38.474dB at 3GHz and 29.125dB at 5.75GHz. For the transmitting path the insertion losses were 0.916dB at 3GHz and 1.162dB at 5.75GHz and the isolations were 23.259dB at 3GHz and 16.632dB at 5.75GHz. Compared to the symmetric topology the isolations of the receiving path for the asymmetric one were improved by 15.9dB at 3GHz and 11.9dB at 5.75GHz and its insertion loss was increased by about 0.6dB. In addition, P1dB of 21.5 dBm for the transmitting path was obtained, which is increased by 3.86dB compared to the symmetric one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1323-1333
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• 1997

In this paper, we propose an efficient architecture for a high-speed cell concentrator/distributor(HCCD) in an ATM(Asynchronous Transfer Mode) switch and by analyzeing the simulation results evaluate the performance of the proposed architecuture. The proposed HCCD distributes cells from a switch link to local processors, or concentrates cells from local processor s to a switch link. This design is to guarntee a high throughput for the IPC (inter-processor communication) link in a distributed ATM switching system. The HCCD is designed in a moudlar architecture to provide the extensibility and the flexibility. The main characteristics of the HCCD are 1) Adaption of a local CPU in HCCD for improving flexibility of the system, 2) A cell-baced statistical multiplexing function for efficient multiplexing, 3) A cell distribution function based on VPI(Virtual Path Identifier), 4) A bypassing capability for IPC between processor attached to the same HCCD, 5) A multicasting capability for point-to-multipoint communication, 6) A VPI table updating function for the efficient management of links, 7) A self-testing function for detecting system fault.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.5
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• pp.518-525
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• 2005

The paper proposes a novel ZVZCS PWM converter. It enables the main switch to be turned on/off with both zero voltage and zero current, the auxiliary switch to be turned on/off with ZCS, the rectifier diode to be turned on/off with ZVS. Moreover, this proposed soft switching technique is suitable for not only minority carrier device but also majority carrier semiconductor device. Since auxiliary resonant circuit of the proposed boost converter is placed out of the main power path, therefore, there are no voltage and current stresses on the main switch and diode. The operation of the proposed boost converter is explained and analyzed theoretical and experimentally, from a prototype operating at 100KHz.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.799-802
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• 1998

As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.

• Journal of Power Electronics
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• v.12 no.5
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• pp.723-730
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• 2012

This paper presents a new ZVS single phase bridgeless (Power Factor Correction) PFC, using an active clamp to achieve zero-voltage-switching for all main switches and diodes. Since the presented PFC uses a bridgeless rectifier, most of the time, only two semiconductor components are in the main current path, instead of three in conventional single-switch configurations. This property significantly reduces the conduction losses,. Moreover, zero voltage switching removes switching loss of all main switches and diodes. Also, auxiliary switch turns on zero current condition. The presented converter needs just a simple non-isolated gate drive circuitry to drive all switches. The eight stages of each switching period and the design considerations and a control strategy are explained. Finally, the converter operation is verified by simulation and experimental results.

• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.509-514
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• 2009

In this paper, we designed and analyzed 256GB DRAM-based SSD storage using DDR1 memory and PCI-e interface. SSD is a storage system that uses DRAM or NAND Flash as primary storage media. Since the SSD read and write data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices, HDD. Architecture of the proposed SSD system has performance of high speed data processing duo to use multiple RAM disks as primary storage and PCI-e interface bus as communication path of RAM disks. We constructed experimental system with UNIX, Windows/Linux server, SAN Switch, and Ethernet Switch and measured IOPS and bandwidth of proposed SSD using IOmeter. In experimental results, it has been shown that IOPS, 470,000 and bandwidth,800MB/sec of the DDR-1 SSD is better than those of the HDD and Flash-based SSD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.658-660
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• 2004

모바일 멀티미디어 서비스에서는 핸드오프의 효율적인 처리를 통한 QoS를 보장하는 것이 중요하다. 본 논문에서는 기존 핸드오프 기법의 경로 최적화, 회선의 재활용률, 핸드오프 수행시간 등의 문제점을 개선을 위해 Crossover Switch(CX)탐색 기법에 적용되는 기존의 Loose select, Prior path knowledge와 제안한 Hybrid CX 탐색 알고리즘의 성능분석을 위해 C#을 사용하여 시뮬레이터를 구현하고 회선 재이용률, 경로 최적화 정도를 비교분석하였다. 실험결과 제안한 Hybrid CX 탐색 알고리즘이 우수하다는 것을 확인하였다.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.245-246
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• 2008

변전소 모선에서 측정되는 전압, 전류를 기반으로 하는 CB기반 고장거리 추정기법은 배전선의 다중 분기선 때문에 다중개의 고장위치를 추론하는 것은 물론 분기 부하모델의 불확실성으로 인해 거리 계산에 오차를 포함하게 된다. 따라서 본 연구에서는 유비쿼터스 기반의 배전계통 하에서 구간 측정 전압, 전류 및 IED간 정보교환을 통해 얻어지는 전압, 전류 정보를 이용하여 고장경로를 추정하는 IED 기반 고장경로 추정기법을 제안한다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.894-897
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• 1987

Listener echos, which arise in multiple 4-wire loop connections(MLC) during the evolving switched telephone network, impare voice-band data signal transmission performance. This paper first shows the calculation method of the total number of listener echo loops over N 4-wire physical loops and presents the additative law for listener echos. It next demonstrates that about 4 dB should be ensured to Eke the transmission loss of intraoffice call path be minimum for the voice-band data service in a digital local switch.