• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• Women's Health Nursing
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• v.14 no.1
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• pp.12-19
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• 2008

Purpose: This study was to identify the influencing factors in postmenopausal women's bone mineral density (BMD). Method: The sample for the study was 107 postmenopausal women who took the BMD test. For BMD measurement, lumbar spine BMD(L2-5) was measured by Dual-energy X-ray absorptiometry(DEXA). Data was collected by questionnaires on the selected variables such as reproductive factors and life style factors. Result: In reproductive factors, parity shows significant differences with BMD (F=4.16, p=.02). In life style factors, diet (F=3.01, p=.05) and exercise (F=7.39, p=.00) show significant differences with BMD. Excercise, diet and parity accounted for 42.0% of the influencing factors in Postmenopausal Women's Bone Mineral Density. Conclusion: The influencing factors in postmenopausal women's bone mineral density were excercise, diet and parity. In this paper, it is suggested that the influence of reproductive and life style factors in postmenopausal women's BMD should be studied by long term and needs repeated research. This study can be used as foundation material for nursing education program development for osteoporosis prevention and improvement.

• Korean Journal of Animal Reproduction
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• v.25 no.3
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• pp.231-235
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• 2001

Gestation duration of cow is an important economical trait. Shortening the gestation duration decreases the production cost and increases the competitiveness of Hanwoo industry. Thus, this study was carried out to analyse the effect of expected factors on gestation duration and make an alternative idea for reduced gestation duration. Gestation duration was not affected by cow-parity, but significantly affected by farm, Al year and sire. Therefore, reducing the gestation duration of Hanwoo may require both providing optimum feeding environment and nutrition management for cow and selecting optimum sire for AI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.310-317
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• 2006

In this paper, we propose a new sequential message-passing decoding algorithm of low-density parity-check (LDPC) codes by partitioning check nodes. This new decoding algorithm shows better bit error rate(BER) performance than that of the conventional message-passing decoding algorithm, especially for small number of iterations. Analytical results tell us that as the number of partitioned subsets of check nodes increases, the BER performance becomes better. We also derive the recursive equations for mean values of messages at variable nodes by using density evolution with Gaussian approximation. Simulation results also confirm the analytical results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.5
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• pp.1744-1765
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• 2014

A client stores data in the cloud and uses remote data checking (RDC) schemes to check the integrity of the data. The client can detect the corruption of the data using RDC schemes. Recently, robust RDC schemes have integrated forward error-correcting codes (FECs) to ensure the integrity of data while enabling dynamic update operations. Thus, minor data corruption can be recovered by FECs, whereas major data corruption can be detected by spot-checking techniques. However, this requires high communication overhead for dynamic update, because a small update may require the client to download an entire file. The Variable Length Constraint Group (VLCG) scheme overcomes this disadvantage by downloading the RS-encoded parity data for update instead of the entire file. Despite this, it needs to download all the parity data for any minor update. In this paper, we propose an improved RDC scheme in which the communication overhead can be reduced by downloading only a part of the parity data for update while simultaneously ensuring the integrity of the data. Efficiency and security analysis show that the proposed scheme enhances efficiency without any security degradation.

• CELLMED
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• v.5 no.3
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• pp.18.1-18.4
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• 2015

Dysmenorrhea is the most common gynecological disorder in women of reproductive age. The prevalence of menstrual pain is relatively high and has been shown to be related to many factors like age, age at menarche, menstrual cycle regularity, parity, cigarette smoking, and dietary habits etc. This study was conducted to determine the possible link between dysmenorrhea and the factors related to it. We investigated the associated risk factors that could influence menstrual pain. This Cross Sectional Study was conducted at Dept. of OBG, NIUM, Bangalore. The study consisted of 230 women between the ages of 20 - 49 years. Included volunteers were newly married, nulliparious and parous women. The detailed reproductive history was recorded and was analyzed statistically. It was observed that there were only two factors that were influencing Dysmenorrhea namely the early age at menarche and increase parity. It was hypothesis that earlier start to reproductive life in some way decreases the sensitivity of the uterus to prostaglandin, whereas delayed menarche and postponing reproductive life increase sensitivity of the uterus to prostaglandins and cause severe menstrual pain. It is concluded that early age at menarche and high parity decrease menstrual pain.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.196-201
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• 2013

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.11-18
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• 2007

Back propagation algorithm based on a gradient-decent method has been widely used to the training of a neural network. However, this algorithm have some problems such as dropping the minimum value in a local area according to an initial value and setting the number of units in a hidden layer when training the neural network. Accordingly, to solve the above-mentioned problems, this paper proposes a genetic algorithm using the training method of the neural network. Thus, the improved genetic algorithm using a new crossover and mutation method is proposed to discriminate 3 bit parity. Experiments confirm that the proposed system is effective for training speed after demonstrating for generation gap, the number of units in the hidden layer, and the number of individuals.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.