• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.899-902
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• 2003

Chip Pin Parasitic은 실제 Chip Pad에서부터 Bonding Wire를 통한 Package Lead Frame까지를 의미한다. 여기서, Lead Frame 및 Bonding Wire에서 Inductance 및 작은 저항이 보이고, Chip Pad에서의 Capacitance, 그리고 Pad 부터 Ground까지의 Return Path에서 발생하는 저항이 보인다. 이들을 모두 합하면 L, R, C의 Series로 나타낼 수 있다. 본 논문에서는 이런 Chip Pin Parasitic을 추출 하기 위해서 TDR(Time Domain Reflectometer)과 NA(Network Analyzer)를 사용하였는데, TDR의 경우 PCB를 제작하여 Chip을 Board위에 붙인 후 Time Domain에서 측정 하였고 NA의 경우 Pico Probe를 이용하여 Chip pin에 직접 Probing해서 Smith Chart를 통하여 Extraction 값을 추출했다. 이 경우, NA를 이용한 측정이 좀 더 정확한 Parasitic 값을 추출할 수 있으리라 예상되겠지만, 실제로 Chip이 구동하기 위해서는 Board위에 있을 때의 상황도 고려해야 하기 때문에 TDR 추출 값과 NA 추출 값을 모두 비교하였다.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.2
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• pp.49-53
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• 2005

The current drive in a MOSFET is limited by the intrinsic channel resistance. All other parasitic elements in a device structure perform significant functions leading to degradation in the device performance. These other resistances must be less than 10$\%$-20$\%$ of the channel resistance. To meet the necessary requirements, the methodology of separation and quantification of those resistances should be investigated. In this paper, we developed an extraction method for the resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that gathers below the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• Proceedings of the Optical Society of Korea Conference
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• 2007.07a
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• pp.289-290
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• 2007

We have theoretically derived a electrical model and extracted a parasitic parameters of leakage current in InGaN/GaN light emitting diodes (LEDs). The parasitic parameters of our LED are $R_p=10^{10}{\Omega}$, $I_{0,2}=10^{-17}A$ and $n_2=3.6$, which provide information of leakage current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.3
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• pp.116-122
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• 2003

This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method Is based on Finite Element Method(FEM) and expands the conventional FEM by adopting variable division. This method improves the extraction efficiency 50 times when compared to the conventional FEM with equal division. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.1-10
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• 1999

Direct extraction of FET's small signal model parameters needs predetermined parasitic elements usually obtained under forward cold FET conditionl This paper derives analytic intrinsic model for cold FET's and shows that normal cold FET condition can replace forward cold FET condition for extracting parasitic elements. Then, we track the error of hot FET's small signal model bounded by the cold FET condition and examine the validness of cold parasitic resistances by checking the existence of the error minimum.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.5
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.