• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.148-148
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• 2008

Low-k dielectric materials are an alternative plan to improve the signal propagation delay, crosstalk, dynamic power consumption due to resistance and parasitic capacitance generated the decrease of device size. Now, various materials is studied for the next generation. Diethoxymethlysiliane (DEMS) precursor using this study has two ethoxy groups along with one methyl group attached to the silicon atoms. SiCOH thin films were deposited on p-type Si(100) substrate by Plasma Enhanced Chemical Vapor Deposition (PECVD) using DEMS. In this study, we studied the effect of oxygen($O_2$) flow rate for DEMS to characteristics of thin films. The characteristics of thin films deposited using DEMS and $O_2$ evaluated through refractive index, dielectric constant(k), surface roughness, I-V(MIM:Al / SiCOH / Ag), C-V(MIM), deposition rate.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.1
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• pp.88-96
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• 2016

In this paper, the GaN FET based phase-shift full-bridge dc-dc converter design is implemented. Switch characteristics of GaN FET were analyzed in detail by comparing state-of-the-art Si MOSFET. Owing to the low conduction resistance and parasitic capacitance, it is expected to GaN FET based power conversion system has improved performance. However, GaN FET is vulnerable to electric interference due to the relatively low threshold voltage and fast switching transient. Therefore, it is necessary to consider PCB layout to design GaN FET based power system because PCB layout is the main reason of stray inductance. To reduce the electric noise, gate voltage of GaN FET is analyzed according to operation mode of phase-shift full-bridge dc-dc converter. Two 600W phase-shifted full-bridge dc-dc converter are designed based on the result to evaluate effects of stray inductance.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.389-390
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• 2008

The dependence of $f_T$ and $f_{max}$ on the unit finger width is measured and analyzed for $0.13{\mu}m$ MOSFETs. The increase of $f_T$ at narrow width is attributed by the parasitic gate-bulk capacitance, and the decrease of $f_T$ at wide width is generated by the reduction of increasing rate of $g_{mo}$. The increase of $f_{max}$ at narrow width is originated from the abrupt reduction of gate resistance due to the non-quasi-static effect. These analysis results will be valuable information for layout optimization to improve $f_T$ and $f_{max}$.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• The Plant Pathology Journal
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• v.26 no.3
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• pp.209-215
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• 2010

Plant pathogenic oomycetes, such as Phytophthora spp., are the causal agent of the most devastating plant diseases. During infection, these pathogens accomplish parasitic colonization of plants by modulating host defenses through an array of disease effector proteins. These effectors are classified in two classes based on their target sites in the host plant. Apoplastic effectors are secreted into the plant extracellular space, and cytoplasmic effectors are translocated inside the plant cell, through the haustoria that enter inside living host cell. Recent characterization of some oomycete Avr genes showed that they encode effector protein with general modular structure including N-terminal conserved RXLR-DEER motif. More detailed evidences suggest that these AVR effectors are secreted by the pathogenic oomycetes and then translocated into the host plant cell during infection. Recent findings indicated that one of the P. infestans effector, Avrblb2, specifically induces hypersensitive response (HR) in the presence of Solanum bulbocastanum late blight resistance genes Rpi-blb2. On the other hand, another secreted RXLR protein PexRD8 originated from P. infestans suppressed the HCD triggered by the elicitin INF1. In this review, we described recent progress in characterized RXLR effectors in Phytophthora spp. and their dual functions as modulators of host plant immunity.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.11
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• pp.17-22
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• 2000

A novel and robust direct parameter extraction method for hybrid-p equivalent circuit model of HBT is proposed. A new expression that can accurately resolve the base internal resistance from the measured S-parameters is derived, and it is not sensitive to the values of parasitic access inductance values. Based on the expression, six analytical expressions for the other parameters is developed and these expressions for hybrid-p equivalent circuit modeling ensure robust, fast, and reliable parameter extraction.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.38-48
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• 1992

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.1
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• pp.1-11
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• 1999

Hyrdogenated amorphous silicon thin film transistors are used as a pixel switching device of TFT-LCDs and very active research works on a-Si:H TFTs are in progress. Further development of the technology based on a-Si:H TFTs depends on the increased understanding of the device physics and the ability to accurately simulate the characteristics of them. A two-dimensional device simulator based on the realistic and flexible physical models can guide the device designs and their optimizations. A non-uniform finite-difference TFT Simulation Program, TFT2DS has been developed to solve the electronic transport equations for a-Si:H TFTs. In TFT2DS, many of the simplifying assumptions are removed. The developed simulator was used to calculate the transfer and output characteristics of a-Si:H TFTs. The measured data were compared with the simulated ones for verifying the validity of TFT2DS. Also the transient behaviors of a-Si:H TFTs were calculated even if the values of the related parameters are not accurately specified.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.36-46
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• 2010

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.