• Journal of Power Electronics
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• 제12권4호
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• pp.643-653
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• 2012

An interleaved DC/DC converter with series-connected transformers is presented to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two half-bridge converter cells connected in series to reduce the voltage stress of the switches at one-half of the input voltage. The output sides of the two converter cells with interleaved pulse-width modulation are connected in parallel to reduce the ripple current at the output capacitor and to achieve load current sharing. Therefore, the size of the output chokes and the capacitor can be reduced. The output capacitances of the MOSFETs and the resonant inductances are resonant at the transition instant to achieve ZVS turn-on. In addition, the switching losses on the power switches are reduced. Finally, experiments on a laboratory prototype (24V/40A) are provided to demonstrate the performance of the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.210-213
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• 1999

A battery is the device that transforms the chemical energy into the direct-current electrical energy directly without a mechanical process. Unit cells are connected in series to obtain the necessary voltage, while being connected in parallel to organize capacity for load current and to decrease the internal resistance for corresponding the sudden shift of the load current. The circular-current, however, could be occurred when the system is driven in parallel. As a result, the new batteries are heated by over-change and discharge, and the over charge current makes to increase the rust of the positive grid and consequently the shortened life of the new batteris would be shown. In this paper, the internal resistance of charge and discharge will be balanced, through inserting the resistance into the system by way of calculation of the changed amount of internal resistance.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.156-158
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• 2018

The inconsistencies between paralleled battery cells are becoming more considerable issue in high capacity battery applications like electric vehicles. Due to differences in state-of-charge (SOC) and internal resistance within individual cells in parallel, charging or discharging current is not appropriately balanced to each cell in terms of SOC, which may shorten the lifetime or sometimes cause safety issues. In this paper, an intelligent cell-balancing algorithm is proposed to overcome the inconsistency issue especially for paralleled battery cells. In this scheme, SOC information collected in the sub-BMS module is sent to the main-BMS module, where the number of parallel cells to be connected to DC bus is continuously updated based on the suggested SOC comparison rule. To verify the method, operation of the algorithm on 4 paralleled battery cells are simulated on Matlab/Simulink. The simulation result shows that the SOCs of paralleled cells are evenly redistributed. It is expected that the proposed algorithm provides high reliable and prolong the life cycle and working capacity of the battery pack.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.458-464
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• 2017

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2008년도 춘계학술발표대회 논문집
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• pp.241-246
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• 2008

In this paper, we analyze the I-V curve and hot-spot phenomenon caused by solar cells' serial and parallel connected circuit. The mis-match loss of parallel interconnection with low Isc string decrease lower than serially interconnected one and temperature caused by hot-spot does. Also, mis-match loss of parallel interconnection with low Voc string increase more than serially interconnected one. The string having low Voc happened hot-spot phenomenon when open circuit. The bad solar cell in string gives revere bias to good solar cell and make hot-spot phenomenon. If we consider the mis-match loss, when designing PV module and array. the efficiency of PV system might increase.

• 전력전자학회논문지
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• 제6권1호
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• pp.34-42
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• 2001

전지는 화학에너지를 기계적인 처리과정 없이 전기에너지로 직접 전환하는 장치이다. 부하전압과 부하전류의 용량에 따라 단위전지를 직.병렬 연결하여 사용하게 되며, 전지의 병렬운전은 단독운전 보다 전압강하를 더 천천히 발생시키므로 전압강하에 민감한 전력변환장치들의 효율에 밀접한 관계를 가지고 있다. 병렬운전의 필요성과 장점 때문에 대부분의 축전지를 사용하는 시스템은 병렬운전을 하고 있고, 반면에 선.구 축전지 사이에서 순환 전류가 흐르고, 자가방전이 일어나는 단점 또한 가지고 있다. 신 축전지에서 충.방전 전류가 과다하게 흐르는 불평형 현상과 이로 인해 축전지의 수명단축을 일으키게된다. 본 논문에서는 마이크로 프로세서를 사용하여 선.구 축전지 사이의 볼평형 전류를 검출하고 외부저항을 첨가시켜 내부저항의 차이에 대한 감소효과를 얻어 불평형 전류를 보상하였다. 이를 실험을 통해 구현하였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권11호
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• pp.650-656
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• 한국산업융합학회 논문집
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• 제4권4호
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• pp.379-386
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• 2001

The lower toughness or brittle materials for mechanical test lead to the additional requirement that applied displacements be controlled with high resolution. Biaxial tension and shear tester using stepper motor with harmonic driver is shown. The device had to be high resolution so that the crack initiation process of slow extension and steady growth could be examined, Grip plates were connected to a linear bearing and actuator. The actuators consisted of stepper motors with harmonic driver connected to pre-loaded ball screw and nut assemblies. The encoders and motor controllers were connected to a personal computer so that arbitrary displacements histories could he prescribed in normal and tangential directions. The linear bearings were used to react loads perpendicular to their axes while allowing low friction, parallel movement of the attached grips. Load cells measured the reactions normal and tangential. the loads measured the reactions were recorded by the computer.

• 한국전기전자재료학회논문지
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• 제25권9호
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• pp.723-726
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• 2012

A current intensity convertible CLD chip was fabricated using small and large FET cell configuration. Pinch-off current of 8.82 mA and 11.56 mA were obtained for small and large cell in the CLD chip, respectively. Constant current was fairly maintained until the breakdown voltage of 60 V. Measured knee voltage, $V_k$ were 3.8 V and 4.5 V for small and large cell, respectively. We configured current amplifying chip with parallel connection of each cells, by connecting 8 individual large cells in parallel network, 92.0 mA of current was obtained. The pinch-off constant current of CLD chip was varied very linearly with respect to the number of parallel connected cell.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.274-276
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• 2008

This paper proposes an individual charge equalization converter using selective two current paths for series connected lithium-ion battery strings. In the proposed equalizer, a central equalization converter acting as a controllable current source is sequentially connected in parallel with individual batteries through an array of cell selection switches. A flyback converter with a modified rectifier realizes a controllable current source. A central equalization converter is shared by every battery cells through the cell selection switch, instead of a dedicated charge equalizer for each cell. With this configuration, although the proposed equalizer has one dc-dc converter, individual charge equalization can be effectively achieved for the each cell in the strings. Furthermore, since the proposed equalizer would not allocate the separated dc-dc converter to each cell, such that the implementation of great size reduction and low cost can be allowed. In this paper, an optimal power rating design guide is also employed to obtain a minimal balancing size while satisfying equalization requirements. A prototype for eight lithium-ion battery cells is optimally designed and implemented. Experimental results verify that the proposed equalization method has good cell balancing performance showing small size, and low cost.