• 한국정보전자통신기술학회논문지
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• 제10권4호
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• pp.288-294
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• 2017

최근들어 CNN(Convolutional Neural Network)을 이용한 딥러닝 기술이 영상인식 등의 분야에서 널리 활용되고 있다. CNN에서 승산과 가산으로 수행되는 컨볼루션 처리는 단순한 연산이지만 하드웨어로 구현하는 데 문제가 되는 것은 승산을 수행하는데 필요한 계산시간이다. 컴퓨팅 파워의 사용에 문제가 없는 응용분야에서는 문제가 되지 않지만 임베디드용 딥러닝 시스템 등의 구현을 위한 하드웨어 칩설계에서는 많은 제한이 있다. 따라서 본 논문에서는 그레이스케일 영상을 2진영상의 중첩으로 표현한 후, 병렬로 가산만을 이용하여 컨볼루션을 수행하는 병렬가산 알고리즘을 제안하였다. 본 논문에서 새롭게 제안한 알고리즘의 유용성을 확인하기 위한 실험을 통해 처리시간의 감소가 가능한 병렬가산 방식으로 컨볼루션을 수행할 수 있음을 확인하였다.

• 한국전기전자재료학회논문지
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• 제18권9호
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• pp.863-869
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• 2005

We investigated quench characteristics of superconducting elements connected in series and parallel each other. The serial and parallel connections of superconducting elements causes a difficulty in simultaneous quench due to slight difference between their critical current densities. In other to induce simultaneous quench, we fabricated four type circuits; serially connected circuit before parallel connection, the circuit connected in parallel before serial connection, serially connected circuit before parallel connection with reactors, the circuit connected in Parallel before serial connection with reactors. We confirmed that the simultaneous quenches occurred in serial and parallel connections of superconducting elements using reactors. In addition, the power burden of superconducting elements was smaller than those of serial and parallel connections of superconducting elements without reactors.

• 전자공학회논문지B
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• 제33B권3호
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• pp.109-119
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• 1996

We propsoed a multiplexed optical correlation filter method for an optical parallel addition based on symbolic substitution. In the proposed mthod, we used redundant binary number which was easy to minimize the number of the symbolic substitution rules. We chose MACE filter which had very low sidelobes and good correlation peak compared with SDF filter as the optical correlation recognition filter and encoded input numbers properly to increase the discrimination capability. In order to minimize the number of symbolic substitution rules, sixteen input patterns were divided into six groups of the same addition results and six filters for recognizing the input patterns were used. these filters were multiplexed in two MMACE filter planes and the corresponding substitution method was proposed. Through the computer simulation, we confirmed the proposed method was suitable to implement the optical parallel adder.

• ETRI Journal
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• 제31권5호
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

• 한국시뮬레이션학회논문지
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• 제7권1호
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• 제어로봇시스템학회논문지
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• 제5권3호
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• pp.288-296
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• 1999

A force-reflecting hand controller can provide the kinesthetic information obtained from a slave manipulator to the operator of a teleoperation system. The goal is to construct a compact hand controller that can provide large workspace and good force-reflecting capability. This paper presents the design and the analysis of a 6-degree-of-freedom force-reflecting hand controller using fivebar parallel mechanism. The forward kinematics of the fivebar parallel mechanism has been calculated in real-time using three pin-joint sensors in addition to six actuator position sensors. A force decomposition approach is used to compute the Jacobian. To evaluate the characteristics of the fivebar parallel mechanism, it has been compared with the other three parallel mechanisms in terms with workspace and manipulability measure. The hand controller using the fivebar parallel mechanism has been constructed and tested to verify the feasibility of the design concept.

• ETRI Journal
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• 제32권4호
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• pp.555-565
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• 2010

Parallel simulation is an efficient way to cope with long runtimes and high computational requirements in simulations of modern complex integrated electronic circuits and systems. This paper presents an algorithm for parallel simulation based on parallelization in equation formulation and simultaneous calculation of matrix contributions for nonlinear analog elements. In addition, the paper describes the development of a grid interface for a parallel simulator that enables a designer to perform simulations on distant computer clusters. Performances of the developed parallel simulation algorithm are evaluated by simulation of a microelectromechanical system.

• ETRI Journal
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• 제44권2호
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• pp.313-326
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• 2022

This study presents a noble scheme for distributed and parallel simulations with optimized agent placement for simulation instances. The traditional parallel simulation has some limitations in that it does not provide sufficient performance even though using multiple resources. The main reason for this discrepancy is that supporting parallelism inevitably requires additional costs in addition to the base simulation cost. We present a comprehensive study of parallel simulation architectures, execution flows, and characteristics. Then, we identify critical challenges for optimizing large simulations for parallel instances. Based on our cost-benefit analysis, we propose a novel approach to overcome the performance constraints of agent-based parallel simulations. We also propose a solution for eliminating the synchronizing cost among local instances. Our method ensures balanced performance through optimal deployment of agents to local instances and an adaptive agent placement scheme according to the simulation load. Additionally, our empirical evaluation reveals that the proposed model achieves better performance than conventional methods under several conditions.

• 정보처리학회논문지A
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• 제10A권6호
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• pp.671-676
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• 2003

본 논문에서는 고속 병렬 곱셈기에서 속도향상을 위해 부분 곱을 가산하는 과정에 구성되는 CSA(Carry Select Adder) 트리에 새로운 압축기를 적용한 새로운 첫 번째 부분 곱가산(First Partial Product Addition : FPA)를 제안하여 기존의 전가산기를 이용한 병렬가산기보다 부분곱을 계산하는 속도를 약 20% 개선할 수 있게 했다. 새로운 회로는 새로운 FPA 구조를 사용하여 최종 합 CLA 비트를 N/2로 줄인다. 2.5v 0.25um CMOS 기술을 이용하여 제작된 16${\times}$16 곱셈기는 5.14nS의 곱셈 고속을 얻었다. 이 곱셈기의 구조는 파이프라인 설계에 용이하며 고성능을 낸다.

• 한국정보통신학회논문지
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• 제14권4호
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• pp.859-867
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• 2010

본 논문에서는 일반적인 비트기반의 비선형 결합함수를 고속화하기 위하여 워드기반 스트림 암호에서 적용될 워드기반 비선형 결합함수 구조를 제안하였다. 특히, 워드기반 병렬구조를 갖는 PS-WFSR을 제안하였고, 이를 활용하여 비트 기반 비선형 결합함수를 고속화시킨 4가지 형태의 워드기반 병렬형 비선형 결합함수를 다음과 같이 제안하였다. m-병렬 워드기반 비메모리 비선형 결합함수, m-병렬 워드기반 메모리 비선형 결합함수, m-병렬 워드기반 비선형 필터함수, m-병렬 워드기반 클럭조절형 함수를 제안하였고, 마지막으로 m-병렬 워드기반 DRAGON의 병렬 구조를 통하여 그 성능을 분석하였다.