• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.189-198
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• 2008

In this paper, we prove mesh-like networks can be embedded into Petersen-Torus(PT) networks. Once interconnection network G is embedded in H, the parallel algorithm designed in Gcan be applied to interconnection network H. The torus is embedded into PT with dilation 5, link congestion 5 and expansion 1 using one-to-one embedding. The honeycomb mesh is embedded into PT with dilation 5, link congestion 2 and expansion 5/3 using one-to-one embedding. Additional, We derive average dilation. The embedding algorithm could be available in both wormhole routing system and store-and-forward routing system by embedding the generally known Torus and honeycomb mesh networks into PT at 5 or less of dilation and congestion, and the processor throughput could be minimized at simulation through one-to-one.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.2
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• pp.65-74
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• 2002

Recently star networks are considered as attractive alternatives to the widely used hypercube for interconnection networks in parallel processing systems by many researchers. One of the fundamental communication problems on star graph networks is broadcasing In this paper we consider the broadcasting problems in star graph networks using wormhole routing. In wormhole routed system minimizing link contention is more critical for the system performance than the distance between two communicating nodes. We use Hamiltonian paths in star graph to set up link-disjoint communication paths We present a broadcast algorithm in n-dimensional star graph of N(=n!) nodes such that the total completion time is no larger than $([long_n n!]+1)$ steps where $([long_n n!]+1)$ is the lower bound This result is significant improvement over the previous n-1 step broadcasting algorithm.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.440-443
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• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.34 no.2
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• pp.617-626
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• 2014

Lately, losses and damage from natural disasters have been increasing. Researchers across various fields in Korea are trying to come up with a response plan, but research for evacuation plans is still far from satisfactory. Hence this paper proposes a model that could find an optimized evacuation route for when disasters occur over wide areas. Development of the model used methods including the Dijkstra shortest path algorithm, feasible path method, genetic algorithm, and pareto efficiency. Computations used parallel computing (SPMD) for high performance. In addition, the developed model is applied to a virtual network to check the validity. Finally the adaptability of the model is verified on a real network by computating for Gumi 1stNational Industrial Complex. Computation results proved that this model is valid and applicable by comparison of the fitness values for before optimization and after optimization. This research can contribute to routing for responder vehicles as well as planning for evacuation by objective when disasters occur.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.28 no.3
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• pp.183-192
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• 2022

With the growth of the packaging industry, demand on the packaging printing comes in various forms. Customers' orders are diversifying and the standards for quality are increasing. Offset printing is mainly used in the packaging printing since it is easy to print in large quantities. However, productivity of the offset printing decreases when printing various order. This is because it takes time to change colors for each printing unit. Therefore, scheduling that minimizes the color replacement time and shortens the overall makespan is required. By the existing manual method based on workers' experience or intuition, scheduling results may vary for workers and this uncertainty increase the production cost. In this study, we propose an automated scheduling method of parallel offset printing process for packaging printing. We decompose the original problem into assigning and sequencing orders, and ink arrangement for printing problems. Vehicle routing problem and assignment problem are applied to each part. Mixed integer programming is used to model the problem mathematically. But it needs a lot of computational time to solve as the size of the problem grows. So guided local search algorithm is used to solve the problem. Through actual data experiments, we reviewed our method's applicability and role in the field.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• The Journal of the Korea Contents Association
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• v.4 no.4
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• pp.189-196
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• 2004

Most of the recent researches for ATM switches have been based on multistage interconnection network known as regularity and self-routing property. These networks can switch packets simultaneously and in parallel. However, they are blocking networks in the sense that packet is capable of collision with each other Mainly Banyan network have been used for structure. There are several ways to reduce the blocking or to increase the throughput of banyan-type switches: increasing the internal link speeds, placing buffers in each switching node, using multiple path, distributing the load evenly in front of the banyan network and so on. Therefore, this paper proposes the use of recirculating shuffle-exchange network to reduce the blocking and to improve hardware complexity. This structures are recirculating shuffle-exchange network as simplified in hardware complexity and Rank network with tree structure which send only a packet with highest priority to the next network, and recirculate the others to the previous network. after it decides priority number on the Packets transferred to the same destination, The transferred Packets into banyan network use the function of self routing through decomposition and composition algorithm and all they arrive at final destinations. To analyze throughput, waiting time and packet loss ratio according to the size of buffer, the probabilities are modeled by a binomial distribution of packet arrival. If it is 50 percentage of load, the size of buffer is more than 15. It means the acceptable packet loss ratio. Therefore, this paper simplify the hardware complexity as use of recirculating shuffle-exchange network instead of bitonic sorter.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.7
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• pp.159-172
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• 2016

This paper presents a novel algorithm for searching evacuation paths in indoor disaster environments. The proposed method significantly improves the time complexity to find the paths to the evacuation exit by introducing a light-weight Disaster Evacuation Graph (DEG) for a building in terms of the size of the graph. With the DEG, the method also considers load balancing and bottleneck capacity of the paths to the evacuation exit simultaneously. The behavior of the algorithm consists of two phases: horizontal tiering (HT) and vertical tiering (VT). The HT phase finds a possible optimal path from anywhere of a specific floor to the evacuation stairs of the floor. Thus, after finishing the HT phases of all floors in parallel the VT phase begins to integrate all results from the previous HT phases to determine a evacuation path from anywhere of a floor to the safety zone of the building that could be the entrance or the roof of the building. It should be noted that the path produced by the algorithm. And, in order to define the range of graph to process, tiering scheme is used. In order to test the performance of the method, computing times and evacuation times are compared to the existing path searching algorithms. The result shows the proposed method is better than the existing algorithms in terms of the computing time and evacuation time. It is useful in a large-scale building to find the evacuation routes for evacuees quickly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1689-1700
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• 1993

WDM(Wavelength Division Multiplexing) based-on fixed wavelengths is a new means of utilizing the bandwidth of optical fibers. In this Paper, an improved virtual topology called "(a, $\beta$,${\gamma}$) ShuffleNet " is introdced for designing large-scale WDM switches. The proposed one is an architecture created by vertically stacking x planes of a ($\beta$,${\gamma}$) ShuffleNet in parallel via $\beta$r nodes called "bridge nodes" so that N-by-N(N=(x*$\beta$${\gamma}$*${\gamma}$) switching is achieved based on the self-routing algorithm for each ($\beta$,${\gamma}$) ShuffleNet. With the topological parallelism, in contrast to the conventional virtual topologies, the diameter of 2${\gamma}$ hops can be fixed and high utilization and performance are provided while N increases. Such a scalability characteristic allows to design a growable broadband switch. As for the delay, we show that the traffic locality, due to the topological feature. result in low delay characteristics.lay characteristics.