• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• International Journal of Highway Engineering
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• v.15 no.6
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• pp.41-47
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• 2013

PURPOSES : The purpose of this study is about noise which is generated from roads and is consist of irregular frequency variation from low frequency to various band. The existing methods of noise reduction are sound barrier that uses insulation material and absorbing material or have applied passive technology of noise reduction by devices. The total frequency band is needed to apply active noise control. METHODS : In this study applies to the field of road traffic environment, signal processing controller and various analog signal input/output, the amplifier module is based on parallel-core embedded processor designed. DSP performs the control algorithm of the road traffic noise. Noise sources in the open space performance of evaluation were applied. In this study, controller of active signal processor was designed based on the module of audio input/output and main controller of embedded process. The controller of active signal processor operates noise reduction algorithm and performance tests of noise reduction in inside and outside environment were executed. RESULTS : The signal processing controller with OMAP-L137 parallel-core processors as the center, DSP processors in the active control operations dealt with quickly. To maximize the operation speed of an object and ARM processor is external function keys and display for functions and evaluating the performance management system was designed for the purpose of the interface. Therefore the reduction of road traffic noise has established an electronic controller-based noise reduction. CONCLUSIONS : It is shown that noise reduction is effective in the case of pour tonal sound and complex tonal sound below 500Hz by appling to Fx-LMS.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.931-934
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• 1999

For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• Journal of IKEEE
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• v.21 no.1
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• pp.92-95
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• 2017

In this paper, we proposed a way to improve function of small scale GP-GPU. Instead of using superscalar which increase scheduling-complexity, we suggested the application of simple core to maximize GP-GPU performance. Our studies also demonstrated that simplified Stream Processor is one of the way to achieve functional improvement in GP-GPU. In addition, we found that developing of optimal thread-assigning method in Warp Scheduler for specific application improves functional performance of GP-GPU. For examination of GP-GPU functional performance, we suggested the thread-assigning way which coordinated with Deep-Learning system; a part of Neural Network. As a result, we found that functional index in algorithm of Neural Network was increased to 90%, 98% compared with Intel CPU and ARM cortex-A15 4 core respectively.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.2
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• pp.542-558
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• 2023

A digital focus index (DFI) is a value used to determine image focus in scientific apparatus and smart devices. Automatic focus (AF) is an iterative and time-consuming procedure; however, its processing time can be reduced using a general processing unit (GPU) and a multi-core processor (MCP). In this study, parallel architectures of a minimax search algorithm (MSA) are applied to two DFIs: range algorithm (RA) and image contrast (CT). The DFIs are based on a histogram; however, the parallel computation of the histogram is conventionally inefficient because of the bank conflict in shared memory. The parallel architectures of RA and CT are constructed using parallel reduction for MSA, which is performed through parallel relative rating of the image pixel pairs and halved the rating in every step. The array size is then decreased to one, and the minimax is determined at the final reduction. Kernels for the architectures are constructed using open source software to make it relatively platform independent. The kernels are tested in a hexa-core PC and an embedded device using Lenna images of various sizes based on the resolutions of industrial cameras. The performance of the kernels for the DFIs was investigated in terms of processing speed and computational acceleration; the maximum acceleration was 32.6× in the best case and the MCP exhibited a higher performance.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.211-216
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• 2009

As demands for high-definition television (HDTV) increase, the implementation of real-time decoding of high-definition (HD) video becomes an important issue. The data size for HD video is so large that real-time processing of the data is difficult to implement, especially with software. In order to implement a fast moving picture expert group-2 decoder for HDTV, we compose five scenarios that use parallel processing techniques such as data decomposition, task decomposition, and pipelining. Assuming the multi digital signal processor environments, we analyze each scenario in three aspects: decoding speed, L1 memory size, and bandwidth. By comparing the scenarios, we decide the most suitable cases for different situations. We simulate the scenarios in the dual-core and dual-central processing unit environment by using OpenMP and analyze the simulation results.

• Geophysics and Geophysical Exploration
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• v.21 no.4
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• pp.213-219
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• 2018

In this study, we simulated 3D wave propagation modeling using a Xeon Phi x200 processor and compared the parallel computation performance with that using a Xeon CPU. Unlike the 1st generation Xeon Phi coprocessor codenamed Knights Corner, the 2nd generation x200 Xeon Phi processor requires no additional communication between the internal memory and the main memory since it can run an operating system directly. The Xeon Phi x200 processor can run large-scale computation independently, with the large main memory and the high-bandwidth memory. For comparison of parallel computation, we performed the modeling using the MPI (Message Passing Interface) and OpenMP (Open Multi-Processing) libraries. Numerical examples using the SEG/EAGE salt model demonstrated that we can achieve 2.69 to 3.24 times faster modeling performance using the Xeon Phi with a large number of computational cores and high-bandwidth memory compared to that using the 12-core CPU.

• The Journal of the Acoustical Society of Korea
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• v.36 no.6
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• pp.425-435
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• 2017

In this paper, we propose optimization methods for speeding the feedforward network of deep neural networks using NEON SIMD (Single Instruction Multiple Data) parallel instructions and multi-core parallelization on the multi-core ARM processor. As the result of the optimization using SIMD parallel instructions, we present the amount of speed improvement and arithmetic precision stage by stage. Through the optimization using SIMD parallel instructions on the single core, we obtain $2.6{\times}$ speedup over the baseline implementation using C compiler. Furthermore, by parallelizing the single core implementation on the multi-core, we obtain $5.7{\times}{\sim}7.7{\times}$ speedup. The results we obtain show the possibility for applying the arithmetic-intensive deep neural network technology to applications on mobile devices.