• Journal of the Korean Society of Industry Convergence
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• v.27 no.5
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• pp.1099-1109
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• 2024

As a wide range of industries using iron, such as water and sewerage pipes, gas pipelines, heat pipes, electric engines, communication pipes, and oil pipelines, rapidly become active, there is a demand for reliability and low cost of DC power supplies that can prevent corrosion of pipe networks. In particular, high-efficiency corrosion prevention systems due to changes in the perception of carbon emissions and energy saving are essential elements. Therefore, the construction of a switching-type corrosion current controller is being activated. Also, in such systems, DC/DC converters capable of multi-channel current control are demanded for corrosion prevention functions and uniform consumption of sacrificial anodes. This paper proposes a new current supply system for preventing pipeline corrosion using a low-cost SMPS dedicated chip. The proposed method can maintain excellent parallel operation function, protection function, and response speed by configuring a current controller using a hybrid method using analog and digital. The proposed method verified its superiority through simulations and experiments.

• Journal of the Korean Institute of Gas
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• v.5 no.4 s.16
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• pp.21-26
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• 2001

Because of the continuous growth of energy consumption, and also tile tendency to site power lines and pipelines along the same routes, the close proximity of high voltage structures and metallic pipelines has become more and more frequent. Recently, the results of assessment about a system integrity are needed in korea also when a gas pipeline is running parallel with high voltage power line in same submarine tunnel, Therefore, we analyze the system integrity(AC corrosion of pipe, melting of pipeline coating, safety of insulation flange, especially cathodic protection system which are rectifier and CI(cathodic Isolator)) resulting from the influence of high voltage power system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.942-947
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• 2008

A cluster server usually consists of a front end node and multiple backend nodes. Though increasing the number of bookend nodes can result in the more QoS(Quality of Service) streams for clients, the possibility of failures in backend nodes is proportionally increased. The failure causes not only the stop of all streaming service but also the loss of the current playing positions. In this paper, when a backend node becomes a failed state, the recovery mechanisms are studied to support the unceasing streaming service. The basic techniques are hewn as providing very high speed data transfer rates suitable for the video streaming. However, without considering the architecture of cluster-based VOD server, the application of these basic techniques causes the performance bottleneck of the internal network for recovery and also results in the inefficiency CPU usage of backend nodes. To resolve these problems, we propose a new failure recovery mechanism based on the pipeline computing concept.

• Journal of the Korean GEO-environmental Society
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• v.16 no.9
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• pp.43-51
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• 2015

In this paper, a 3D shell-spring model that can perform time history analysis of buried pipelines is used to evaluate the effect of the incident direction of the earthquake motion. When applying harmonic motions, it is shown that the period of vibration has pronounced influence on the response of buried pipelines. With decrease in the period, the curvature of the pipeline and corresponding response are shown to increase. To evaluate the effect of the incident angle, the motions are applied in the direction of the pipleline, horizontal, and vertical planes. When the motion is applied parallel to the direction of the pipeline, it only induces bending strains and therefore, the response is the lowest. Under motions subjected in horizontal and vertical planes at an angle of $45^{\circ}$ from the longitudinal axis of the buried pipeline, the axial deformation is shown to contribute greatly to the response of the pipelines. When imposing two-components simultaneously, the calculated response is similar to the case where only single-component is imposed. It is because one component only induces bending strain, resulting in very small increase in the response. The trend of the response is shown to be quite similar for recorded motions. Therefore, it is concluded that use of a single-component is sufficient for estimation of the longitudinal response of buried pipelines.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• The Journal of the Korea Contents Association
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• v.13 no.2
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• pp.44-51
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• 2013

Routers should perform fast IP address lookup for Internet to provide high-speed service. In this paper, we present a hybrid parallel IP address lookup structure composed of four-stage pipeline. It achieves parallelism at low cost by using multiple SRAMs in stage 2 and partitioned TCAMs in stage 3, and improves the performance through pipelining. The smart distributor in stage 1 does not transfer any IP address identical to previous one toward the next stage, but only uses the result of the previous lookup. So it improves throughput of lookup by caching effects, and decreases the access conflict to TCAM bank in stage 3 as well. In the last stage, the reorder buffer rearranges the completed IP addresses according to the input order. We evaluate the performance of our parallel pipelined IP lookup structure comparing with previous hybrid structure, using the real routing table and traffic distributions generated by Zipf's law.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.