• Journal of the Korean Institute of Gas
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• v.12 no.4
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• pp.8-13
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• 2008

The stray current interference problem could induce the corrosion of near-by structure and rail itself. Many efforts has been concentrated on the reduction of the interference. In this work the influences of separation distance, soil resistivity, pipe coating resistance, leak resistance of rail were studied using the numerical analysis methods. These analysis could be used to estimate the sensitivity of each variables in the study of the mitigation method and their numerical analysis.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.99-106
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• 2004

In this Paper, the matched filter for searching initial synchronization in DSSS (direct sequence spread spectrum) receiver is studied. The matched filter with a single data flow path is described which can be presented by HDL (Hardware Description Language). In order to improve the processing time of operations for the filter, equations are arranged to represent two data flow paths and the associated hardware model is proposed. The model has an architecture based on parallelism and pipeline for fast processing, in which two data flow paths with a series of memory, multiplier and accumulator are placed in parallel. The performance of the model is analyzed and compared with the matched filter with a single data flow path.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.35-41
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• 2000

In this paper, the multiplicative algorithm of two polynomals over finite field GF(2$^{m}$ ) is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. This multiplier is consisted of three operation unit: multiplicative operation unit, the modular operation unit, the primitive irreducible operation unit. The multiplicative operation unit is composed of AND gate, X-OR gate and multiplexer. The modular operation unit is constructed by AND gate, X-OR gate. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and interconnection of the cells are regular, well-suited for VLSI realization.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.87-93
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• 1989

Squared-error Pattern Clustering algorithm used in unsupervised pattern recognition and image processing application demands substantial processing time for operation of feature vector matrix. So, this paper propose the fast squared-error Pattern Clustering Processor using the Residue Number System which have been the nature of parallel processing and pipeline. The proposed Squared-error Pattern Clustering Processor illustrate satisfiable error rate for Cluster number which can be divide meaningful region and about 200 times faster than 80287 coprocessor from experiments result of image segmentation. In this result, it is useful to real-time processing application for large data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.108-111
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• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.12
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• pp.632-641
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• 2001

In this paper, we introduce new methods for hiding computation overheads involved in load redistributing for parallel computer of hypercube, mesh and tree topologies. The basic idea is either coalescing some phases of load redistributing to overlap the transfer on different links or dividing each phase into steps to pipeline the transfer of load unit by unit for maximum utilization of links. They proved effective in making links busy transmitting load as soon as possible, hence reducing the computation overheads involved in balancing. Proposed techniques experimented on hypercube, mesh or tree topologies reduce communication overheads by 20% to 50% compared with known methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.41-44
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• 2013

As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.6
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• pp.556-565
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• 1991

Using the WDZ decomposition algorithm, a parallel algorithm is presented for solving the linear system Ax=b which has an nxn nonsingular tridiagonal matrix. For implementing this algorithm a CAM systolic arrary is proposed, and each processing element of this array has its own CAM to store the nonzero elements of the tridiagonal matrix. In order to evaluate this array the algorithm presented is compared to theis compared to the LU decomposition algorithm. It is found that the execution time of the algorithm presented is reduced to about 1/4 than that of the LU decomposition algorithm. If each computation process step can be dome in one time unit, the system of eqations is solved in a systolic fashion without central control is obtained in 2n+1 time steps.

• Proceedings of the KIEE Conference
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• summer
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• pp.1367-1369
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• 2004

When an underground pipeline runs parallel with subway DC electrification system, it suffers from stray current corrosion caused by the stray current from the rails negative returns. Perforation due to the stray current corrosion may bring about disastrous accidents such even in cathodically protected systems. Traditionally, bonding methods such as direct drainage, polarized drainage and forced drainage have been used in order to mitigate the damage on pipelines. In particular, the forced drainage method is widely adopted in Busan. In this paper, we report the real-time measurement data of the pipe-to-soil potential variation in the presence and absence of the IR compensation. The drainage current variation was also measured using the Stray Current Logger developed. By analyzing them, the problems of current countermeasures for stray current corrosion are discussed.