• 한국자동차공학회논문집
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• 제10권5호
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• pp.121-128
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• 2002

In this paper, the fuel economy of plug-in type hybrid electric vehicle is investigated through simulation. For the simulation study, 2 shaft type parallel hybrid powertrain is chosen and its operation modes are described. The operation algorithm which yields operation points of minimal fuel cost is suggested. Dynamic model fur operation of HEV and simulation procedure is described. Simulation results of fuel economy is compared to non plug-in type HEV as well as conventional vehicle. With total driving distance of 37km and full usage of 2kwh of electric energy stored in battery pack, plug-in type HEV shows 28-30% improved fuel economy compared to non plug-in type HEV and 86-93% improved fuel economy compared to conventional vehicle.

• 한국인터넷방송통신학회논문지
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• 제11권5호
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• pp.27-33
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• 2011

디지털 통신 시스템에서 채널에서 발생되는 ISI(Inter-Symbol Interference)를 줄이기 위해 사용되는 적응 등화기의 알고리즘으로 MCMA(Constant Modulus Algorithm)가 있다. MCMA는 비교적 간단한 연산량을 갖지만 어느 정도 적당한 수렴율과 정상 상태의 MSE(mean square error)를 가지므로 본 논문에서는 이를 개선키 위해 병렬 구조를 갖는 등화 방식을 제안하며, MCMA(Modified Constant Modulus Algorithm)과 MDD(Modified Decision Directed Algorithm)으로 구성이 되어있다. 제안 방식에서는 4-QAM 좌표와 16-QAM 좌표의 관계를 이용한, 새로운 비용 함수를 정의 하고, 만약 수신된 신호에 오프셋이 발생할 때, MCMA의 성능이 저하되므로 이를 극복하기 위해서 본 논문에서는 MDD(Modified Decision Direct) 알고리즘과 결합한 병렬형 구조를 적용하므로서 기존의 MCMA보다 빠른 수렴 속도와 낮은 MSE를 갖는 개선된 성능을 얻을 수 있음을 컴퓨터 시뮬레이션으로 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• 한국멀티미디어학회:학술대회논문집
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• 한국멀티미디어학회 2000년도 춘계학술발표논문집
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• 전자공학회논문지B
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• 제31B권9호
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• pp.76-84
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• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.

• 전력전자학회논문지
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• 제15권4호
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• pp.296-308
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• 2010

본 논문은 영구자석형 동기발전기를 이용한 풍력발전 시스템의 3병렬 운전과 계통연계 기술을 제안한다. 영구자석형 풍력발전 시스템에서 back-to-back 컨버터는 발전기와 계통에 직접 연결되므로 시스템 정격에 준하는 전력 반도체 소자와 필터가 요구된다. 본 논문은 시스템의 전력변환부를 3병렬로 연결하고 병렬 운전에 의해 발생할 수 있는 순환 전류는 적절한 내부 인덕터 선정으로 해결한다. 낮은 스위칭 주파수로 운전되는 대용량 풍력발전 시스템의 THD 규정을 만족시키기 위해 최적 설계된 LCL필터를 사용하고 LCL필터에 의해 발생할 수 있는 공진 문제는 전력이론을 통한 능동 댐핑 기법을 통하여 추가적인 손실 없이 보상한다. 또한 계통 왜곡 및 불평형 시 발생할 수 있는 전력 품질의 문제는 추가적인 보상 알고리즘을 적용하여 향상시킨다. 시뮬레이션 및 실험을 통하여 병렬 운전 시스템과 알고리즘의 타당성을 검증한다.

• 한국통신학회논문지
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• 제21권1호
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• pp.144-154
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• 1996

Proposed numerous algorithms for the policing function have mainly focused on their performances. Besides their performance evaluation, however, the VLSI-implementation of these algorithms is worth consideration as well. Although, no algorithms for the policing function have been standardized up to now, ITU-T I.371 suggests two examples of algorithms, the Virtual Scheduling Algorithm (VSA) and the Continuous State Leaky Bucket algorithm. In this paper, we suggest the architecture of a policing device implementing the VSA among various algorithms for the peak cell rate policing and discuss some issues on the implementation. We also present how to select the policing modes of the two devices used to realize various policing schemes and show the experimental results obtained under four different peak cell rate values to confirm that the device performs the policing function satisfactorily. We exploit the priority encoder to run the algorithm in parallel instead of sequentially, which reduces the operation time to a great extent.

• 전기학회논문지
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• 제56권10호
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• pp.1721-1730
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• 2007

SThis paper proposes a new dispatch scheduling algorithm in interconnected regional system operations. The dispatch scheduling formulated as mixed integer non-linear programming (MINLP) problem can efficiently be computed by generalized Benders decomposition (GBD) algorithm. GBD guarantees adequate computation speed and solution convergency since it decomposes a primal problem into a master problem and subproblems for simplicity. In addition, the inter-temporal optimal power flow (OPF) subproblem of the dispatch scheduling problem is comprised of various variables and constraints considering time-continuity and it makes the inter-temporal OPF complex due to increased dimensions of the optimization problem. In this paper, regional decomposition technique based on auxiliary problem principle (APP) algorithm is introduced to obtain efficient inter-temporal OPF solution through the parallel implementation. In addition, it can find the most economic dispatch schedule incorporating power transaction without private information open. Therefore, it can be expanded as an efficient dispatch scheduling model for interconnected system operation.

• 한국경영과학회지
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• 제27권2호
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• pp.97-109
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• 2002

Manufacturing environments in the real world are subject to many sources of change and uncertainty, such as new job releases, job cancellations, a chance in the processing time or start time of some operation. Thus, the realistic scheduling method should Properly reflect these dynamic environment. Based on the release times of jobs, JSSP (Job Shoe Scheduling Problem) can be classified as static and dynamic scheduling problem. In this research, we mainly consider the dynamic JSSP with continually arriving jobs. The goal of this research is to develop an efficient scheduling method based on GA (Genetic Algorithm) to address dynamic JSSP. we designed scheduling method based on SGA (Sing1e Genetic Algorithm) and PGA (Parallel Genetic Algorithm) The scheduling method based on GA is extended to address dynamic JSSP. Then, This algorithms are tested for scheduling and rescheduling in dynamic JSSP. The results is compared with dispatching rule. In comparison to dispatching rule, the GA approach produces better scheduling performance.

• Journal of the Optical Society of Korea
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• 제17권5호
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• pp.362-370
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• 2013

In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.