• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.173-176
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• 2000

In this study, a new multimedia data converter is proposed. Also the PC interfacing met hod using the parallel port of is suggested. The image compression/decompression is based on the JPEG algorithm, which is widely used for an effective compression in the image processing industry. The suggested interfacing method is based on the IEEE1284 and IEEE1284.3 protocol, which is a standard in the PC's parallel port interface.

• Communications of the Korean Mathematical Society
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• v.10 no.3
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• pp.735-750
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• 1995

We present a domain decomposition algorithm for solving large sparse linear systems of equations arising from queuing networks. Such techniques are attractive since the problems in subdomains can be solved independently by parallel processors. Many of the methods proposed so far use some form of the preconditioned conjugate gradient method to deal with one large interface problem between subdomains. However, in this paper, we propose a "nested" domain decomposition method where the subsystems governing the interfaces are small enough so that they are easily solvable by direct methods on machines with many parallel processors. Convergence of the algorithms is also shown.lso shown.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.743-744
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• 2006

This paper presents implementation of parallel processing system for image processing. The parallel processing system proposed consisted of 16 processing elements, and multi-access memory system, and interface modules. The multi-access memory system we introduced is made up of a memory module selection, a data routing module, and an address calculation and routing module.

• Journal of Information Processing Systems
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• v.4 no.4
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1545-1548
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• 1997

A Force-refecting hand controller can provide the kinesthetic information obtained from a slave manipulator to the operator of a teleoperation system. This thesis presents the desgn and the analysis of a 6-degree-of-freedom force-reflecting hand controller using fivebar parallel mechanism. The goal of this thesis is to construct a superior hand controller that can provide large workspace and good force-reflecting ability. The forward kinematics of the fivebar paprallel mechanism has been calculated in real-time using three pin-joint sensors in addition to six actuator position sensors. A force decomposition approach is used to comput the Jacobin. To analyze the characteristics of the fivebar parallel mechanism, it has been compared with the other three parallel mechanisms in terms with workspace and manipulability measure. The force-reflecting hand controller using the fivebar parallel mechanism has been constructed and tested to verify the feasibility of the design concept.

• 한국전산유체공학회:학술대회논문집
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• 1998.11a
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• pp.147-152
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• 1998

2-D flow fields are studied by using a shared memory parallel computer with a parallel flow analysis program which uses domain decomposition method and MPI library for data exchange at overlapped interface. Especially, effects of directional domain decomposition on parallel efficiency are studied for 2-D Lid-Driven cavity flow and flow through square cavity. It is known from the present study that domain decomposition along the main flow direction gives better parallel efficiency in 1-D partitioning than along the other direction. 2-D partitioning, however, is less sensitive to flow directions and gives good parallel efficiency for most of the cases considered.

• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.455-464
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• 2001

For future multimedia services, one of the most crucial issues is building an access network that can accommodate multimedia services in subscriber network. The VB5.2 interface of B-ISDN located between an access network and a service node allows dynamic allocation and release of ATM resources. The SG 13 of ITU-T is standardizing the B-BCC protocol, which is sequentially interworked with signaling protocols in the service node. To minimize a connection setup delay of the sequential interworking mode, we proposed the parallel interworking model in which the SN executes simultaneously the connection control protocol of VB5.2 interface and signaling protocol. We simulate two interworking models in terms of a connection setup delay and a completion ratio. The results of simulation show that our proposed parallel interworking model for the VB5.2 interface reduces the setup delay and has the similar completion ratio compared to the sequential interworking model. however, the connection setup delay of parallel interworking model becomes about seven tenths of that of the sequential interworking model and the improvement become larger as the arrival rate increased.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of Korea Society of Industrial Information Systems
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• v.5 no.2
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• pp.22-31
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• 2000

The VB5.2 interface of B-lSDN, that is located between an access network and a service node, allows dynamic allocation and release of ATM resources. In this paper, we propose the B-ANCC protocol of the VB5.2 interface to minimize the overall connection setup delay by introducing the access network. The B-ANCC protocol enhances the B-BCC protocol and adopts a parallel interworking function with signaling protocols in the service node. To confirm the correctness of the proposed B-ANCC protocol, we validate it using the automated validation tool, SPIN. We analyze and simulate the sequential interworking model based on the B-BCC protocol and the parallel interworking model based on the B-ANCC protocol, in terms of a connection setup delay and a completion ratio. It is shown that our proposed parallel interworking model with B-ANCC reduces a setup delay and improves a completion ratio compared to the sequential interworking model with B-BCC.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.3
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• pp.319-328
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• 2000

The Message-Passing Interface(MPI) is a standard interface for parallel programming environment, based on that application programs run on the processors of a parallel computer. Processor nodes execute processes consisting the program by passing messages to one another. During executing, however, if a fault occurs on a processor node or a process, this will result an inconsistent state, and consequently, the whole program will have to be stopped. To solve this problem, in this paper, we propose a fault-tolerant message passing interface(FT-MPI) by adding a fault manager module to MPI. The proposed FT-MPI does not need any hardware support, and each application program based on MPI can run on the FT-MPI without any modification. The proposed fault tolerance scheme uses the so-called hot-spare process duplication method, and verified by simulations that application programs run despite of any fault with less than 5% overhead on execution time.