• Journal of Advanced Navigation Technology
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• v.17 no.2
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• pp.202-207
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• 2013

In this paper, a high dividing ratio unequal power divider using parallel connection transmission line is presented. Because a very low impedance transmission line can't implement a microstrip technology, this can fabricate a parallel connection transmission line with high impedance. When we design a high dividing ratio divider, we need the very low impedance line. The parallel connection transmission line could be implemented to obtain a low impedance line characteristic. To validity this approach, we are implemented a 10:1 unequal divider at center frequency 1 GHz. The performances of power divider agree with simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.6
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• pp.105-112
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• 2010

Recently, wireless communication systems have been developed and the circuits which operate with the broad-band for multiband uses were introduced. However, broad-band circuits have problems that inevitably increase the size. Dual-band circuit operates only two frequency, therefore, it will be able to miniaturize through unnecessary decreased elements. The Wilkinson power divider is the one of the most commonly used components in wireless communication system for power division. Nowaday, the Wilkinson power divider is also demanded dual-band. In this paper, I propose miniaturized dual-band Wilkinson power divider operating at 2.45 GHz and 5.2 GHz for IEEE 802.11n standard. Proposed dual-band Wilkinson power divider is used in parallel stub line. The design is accomplished by transforming the electrical length and impedance of the quarter wave sections of the conventional Wilkinson power divider into dual band ${\pi}$-shaped sections.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.9
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• pp.446-451
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• 2006

The output voltage value of AC high voltage source has been usually measured by employing the high voltage divider of inductive or capacitive type. In the study, we have developed a new method for measuring the output voltage up to 60kV using parallel plates electrode and electric field sensor, which are constructed by home-made. Unlikely the conventional method using a high voltage divider, this developed method makes it possible to extend the range of output voltage from known low voltage measurement to high voltage measurement. From the linearity measured between electric field and applied voltage in the output voltage range of 1kV-30kV, the output voltage value up to 60kV can be obtained by the electric field measurement using the electric field sensor. The output voltage value obtained using the method is consistent with that obtained using high voltage divider within corresponding uncertainties.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.273-277
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• 2003

This paper presents a structure of the Wilkinson power divider that can suppress the 9ea harmonic output. The power divider consists of ${\lambda}/4n$ open stubs, which are located at the $3{\lambda}/4$ branches and parallel connection of resistor which shunts the output ports. Experimental results show that this power divider suppresses from 1st to 9th harmonic components to less than -37dB, while maintaining the characteristics of a conventional Wilkinson power divider; featuring an equal power split, a simultaneous impedance matching at all ports and a good isolation between output ports. these results agree quite well with the simulation results.

• Journal of Advanced Navigation Technology
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• v.23 no.4
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• pp.309-315
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• 2019

This paper proposes an implementation of unequal power divider with 1:3 and 1:4 splitting ratio in multi-section structure using CPW and offset coupled transmission line. The power divider consists of a multi-section transmission line and a circuit with parallel capacitors and resistors. A multi-section transmission line was implemented by decomposing a ${\lambda}/4$ single transmission line terminated by an arbitrary impedance and converging it with a multi-section transmission line shorter than $90^{\circ}$ electrical length, and RC parallel circuits were connected between transmission lines to obtain reflection coefficient of output port and isolation characteristics between the output port. In this way, it was confirmed that the transmission lines at the unequal power divider designed at 2 GHz were shorter than ${\lambda}/4$ and implemented at least 27% less than the conventional ones, and that the broadband characteristics could be obtained.

• Journal of electromagnetic engineering and science
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• v.10 no.1
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• pp.35-38
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• 2010

A fully integrated parallel-coupled 6-GHz quadrature voltage-controlled oscillator (QVCO) has been designed. The symmetrical parallel-coupled quadrature VCO is implemented using 0.13-${\mu}m$ CMOS process. The measured phase noise is -101.05 dBc/Hz at an offset frequency of 1 MHz. The tuning range of 710 MHz is achieved with a control voltage ranging from 0.3 to 1.4 V. The average output phase error is about $1.26^{\circ}$ including cables and connectors. The QVCO dissipates 10 mA including buffer from the 1.5 V supply voltage. The output characteristic of the differential injection-locked frequency divider (DILFD), which has similar topology to the QVCO, is presented.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.1-7
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• 1997

In ahigh power amplifier design, power combiner/divider is used to connect low power amplifiers in parallel. The raidal structure of the powe combiner/divider has not only a good characteristics of port-to-port isolation but also an advantage of giving a redundancy to the structure itself by using RF switches. The parastics of a power resistor, that would be a problem in design process, are removed by both slot lines and cavity resonators, and the comon node in the circuit is rdesigned as a planar topology, and thus a new type of 4-way radial power combiner/divider is accomplished at 1840 ~ 1870 MH PCS frequency band. The insertion loss, reflection, and isolation characteristics of 40way radial power combiner/divider which can be adaptable to PCS system in this thesis are -0.3dB, -24dB,a dn -27dB respectively.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.299-304
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• 2020

This paper proposes the design of circular sector shaped power divider-combiner with a planar structure. This structure can be constructed in series, and due to the circular sector shape, it is possible to simplify circuit configuration and improve the amplitude and phase balanced characteristics of the output. It has a simple input matching circuit and an RC parallel circuit was inserted between the output ports to improve the reflection coefficient and isolation of the output. Since the designed divider-combiner are structurally designed in a symmetrical shape of a sector, even if the output ports are composed of two or four output ports, they have excellent characteristics with an amplitude balance of ± 0.1 dB and a phase balance of ± 1o between outputs. To prove these characteristics, it was confirmed that the characteristics of the planar power divider-combiner fabricated at an operating frequency of 2 GHz are in good agreement with the simulation.