• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.3
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• pp.288-296
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• 1999

A force-reflecting hand controller can provide the kinesthetic information obtained from a slave manipulator to the operator of a teleoperation system. The goal is to construct a compact hand controller that can provide large workspace and good force-reflecting capability. This paper presents the design and the analysis of a 6-degree-of-freedom force-reflecting hand controller using fivebar parallel mechanism. The forward kinematics of the fivebar parallel mechanism has been calculated in real-time using three pin-joint sensors in addition to six actuator position sensors. A force decomposition approach is used to compute the Jacobian. To evaluate the characteristics of the fivebar parallel mechanism, it has been compared with the other three parallel mechanisms in terms with workspace and manipulability measure. The hand controller using the fivebar parallel mechanism has been constructed and tested to verify the feasibility of the design concept.

• Particle and aerosol research
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• v.8 no.2
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• pp.75-81
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• 2012

The strength of lumped cokes can be represented by some index numbers. Although some indexes are suggested, these indexes are not enough to enlighten fracture mechanism. To find essential mechanism, a computational way, discrete element method, is applied to the uniaxial compression test for cylindrical specimen. The cylindrical specimen is a kind of lumped particle mass with parallel bonding that will be broken when the normal stress and shear stress is over a critical value. It is revealed that the primary factors for cokes fracture are parallel spring constant, parallel bond strength, bonding radius and packing ratio the parallel bond strength and radius of the parallel combination the packing density. Especially, parallel spring constant is directly related with elastic constant and yield strength.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.5
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• pp.883-890
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• 2001

In practical design studies, most of designers solve multidisciplinary problems with large size and complex design system. These multidisciplinary problems have hundreds of analysis and thousands of variables. The sequence of process to solve these problems affects the speed of total design cycle. Thus it is very important for designer to reorder the original design processes to minimize total computational cost. This is accomplished by decomposing large multidisciplinary problem into several multidisciplinary analysis subsystem (MDASS) and processing it in parallel. This paper proposes new strategy for parallel decomposition of multidisciplinary problem to raise design efficiency by using genetic algorithm and shows the relationship between decomposition and multidisciplinary design optimization (MDO) methodology.

• Electronics and Telecommunications Trends
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• v.4 no.1
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• pp.93-117
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• 1989

Computational Geometry is concerned with the design and analysis of computational algorithms which solve geometry problems. Geometry problems have a large number of applications areas such as pattern recognition, image processing, computer graphics, VLSI design and statistics since they involve inherently geometric problems for which efficient algorithms have to be developed. Several parallel algorithms, based on various parallel computation models, have been proposed for solving geometric problems. We review the current status of the parallel algorithms in computational geometry.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.9
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• pp.1706-1713
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• 2009

In this paper, a parallel operation algorithm for high power PEMFC generation systems is proposed. According to increasing the capacity of fuel cell systems with several fuel cell stacks, the different dynamic characteristics of each fuel cell stack effect on imbalance of load sharing and current distribution, so that a robust parallel operation algorithm is desired. Therefore, a power-sharing technique is developed and explained in order to design an optimal distributed PEMFC generation system. In addition, an optimal controller design procedure for the proposed parallel operation algorithm is introduced, along with informative simulations and experimental results.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• The Journal of Korea Robotics Society
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• v.11 no.4
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• pp.248-255
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• 2016

Machining error makes the uncertainty of dimensional accuracy of the kinematic structure of a parallel robot system, which makes the uncertainty of kinematic accuracy of the end-effector of the parallel robot system. In this paper, the tendency of trajectory tracking error caused by the tolerance of design parameters of the parallel robot is analyzed. For this purpose, all the position errors are analyzed as the manipulator is moved on the target trajectory. X, Y, Z components of the trajectory errors are analyzed respectively, as well as resultant errors, which give the designer of the manipulator the intuitive and deep understanding on the effects of each design parameter to the trajectory tracking errors caused by the uncertainty of dimensional accuracy. The research results shows which design parameters are critically sensitive to the trajectory tracking error and the tendency of the trajectory tracking error caused by them.

• Journal of the Korean Society of Industry Convergence
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• v.10 no.4
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• pp.227-233
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• 2007

In case of design of a rectifier to supply high current, To select switching frequency of semiconductor switches affect absolutely the design of the LC filter value in an power conversion circuit. The conventional rectifier by using MOSFET is no use in high current equipments because of small drain-source current. To solve this problem, this paper proposes to design of high capacity rectifier by parallel driving of MOSFET in the single half bridge DC-DC converter. This method can be able to develop high current rectifier by distributed drain-source current. The proposed scheme is able to expect a decrease in size, weight and cost of production by decreasing the LC filter value and increasing maximumly the switching frequency. The validity of the proposed parallel driving strategy is verified through computer-aided simulations and experimental results.