• Title/Summary/Keyword: Parallel Test Structure

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Wind loads on industrial solar panel arrays and supporting roof structure

  • Wood, Graeme S.;Denoon, Roy O.;Kwok, Kenny C.S.
    • Wind and Structures
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    • v.4 no.6
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    • pp.481-494
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    • 2001
  • Wind tunnel pressure tests were conducted on a 1:100 scale model of a large industrial building with solar panels mounted parallel to the flat roof. The model form was chosen to have the same aspect ratio as the Texas Tech University test building. Pressures were simultaneously measured on the roof, and on the topside and underside of the solar panel, the latter two combining to produce a nett panel pressure. For the configurations tested, varying both the lateral spacing between the panels and the height of the panels above the roof surface had little influence on the measured pressures, except at the leading edge. The orientation of the panels with respect to the wind flow and the proximity of the panels to the leading edge had a greater effect on the measured pressure distributions. The pressure coefficients are compared against the results for the roof with no panels attached. The model results with no panels attached agreed well with full-scale results from the Texas Tech test building.

Development of Common Database for the Application Programs of Distribution Management System (배전운영시스템용 응용 프로그램을 위한 공통 데이터베이스 구축)

  • Yun, Sang-Yun;Chu, Chul-Min;Kwan, Seong-Chul;Lee, Hak-Ju
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.9
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    • pp.1199-1208
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    • 2013
  • In recent years, the development of application programs for distribution system analysis and control has been essential part for distribution management system (DMS). In this paper, we propose the common database for application programs of distribution management system. The proposed database model has several characteristics as followings. First, the proposed database model is designed for the common use of almost the whole distribution application software. The static equipment model and dynamic type tables are mixed and the parallel table structure is applied. Second, the linked list structure of database are used for the fast processing of applications. The database model includes the hierarchy and non-hierarchy distribution system structure. Third, the reduction method of distribution database is applied. For this, we present the network reduction rules. The basic concept of reduction rules are the electrical unification of successive line section which has not lateral branches and the removal of simple lateral branches which has no devices and other laterals. Proposed database model is tested for the Jeju system of Korea Electric Power Corporation (KEPCO). Through the test, we verified that the proposed database structure can be effectively used to accomplish the distribution system operation.

Scalable RDFS Reasoning Using the Graph Structure of In-Memory based Parallel Computing (인메모리 기반 병렬 컴퓨팅 그래프 구조를 이용한 대용량 RDFS 추론)

  • Jeon, MyungJoong;So, ChiSeoung;Jagvaral, Batselem;Kim, KangPil;Kim, Jin;Hong, JinYoung;Park, YoungTack
    • Journal of KIISE
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    • v.42 no.8
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    • pp.998-1009
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    • 2015
  • In recent years, there has been a growing interest in RDFS Inference to build a rich knowledge base. However, it is difficult to improve the inference performance with large data by using a single machine. Therefore, researchers are investigating the development of a RDFS inference engine for a distributed computing environment. However, the existing inference engines cannot process data in real-time, are difficult to implement, and are vulnerable to repetitive tasks. In order to overcome these problems, we propose a method to construct an in-memory distributed inference engine that uses a parallel graph structure. In general, the ontology based on a triple structure possesses a graph structure. Thus, it is intuitive to design a graph structure-based inference engine. Moreover, the RDFS inference rule can be implemented by utilizing the operator of the graph structure, and we can thus design the inference engine according to the graph structure, and not the structure of the data table. In this study, we evaluate the proposed inference engine by using the LUBM1000 and LUBM3000 data to test the speed of the inference. The results of our experiment indicate that the proposed in-memory distributed inference engine achieved a performance of about 10 times faster than an in-storage inference engine.

Design of a Bounded-wave EMP Simulator Antenna (Bounded-wave EMP Simulator 안테나의 설계)

  • Sun, Da-Young;Choi, Hak-Keun;Lim, Seong-Bin;Jang, Jae-Woong;Kim, Tae-Yoon;Choi, Geun-Kyung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.11 no.5
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    • pp.87-93
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    • 2011
  • A threat of the EMP(Electromagnetic Pulse) is recently increasing, so the development of electromagnetic security technology against the EMP is needed. However, the state of the domestic electromagnetic security technology against the EMP is lower level than the foreign. In this paper, the bounded-wave EMP simulator antenna for the development of electromagnetic security technology against a threat of the EMP is designed. The structure of the designed antenna is from a sort of the basic form of the bounded-wave EMP simulator such as a parallel-plate simulator for testing EMP immunity performance within the EUT(Equipment Under Test). The design processes of the designed simulator is including wave launcher, transmission line and termination taper. In the working volume of the designed antenna, the test object within 30 cm is forming predominant TEM field, so it is confirmed that the designed EMP simulator antenna can be used as the EMP simulator.

A study on the parallel processing of the avionic system computer using multi RISC processors (다중 RISC 프로세서를 이용한 항공전자시스템컴퓨터 병렬처리기법 연구)

  • Lee, Jae-Uk;Lee, Sung-Soo;Kim, Young-Taek;Yang, Seung-Yul;Kim, Bong-Gyu;Hwang, Sang-Hyun;Park, Deok-Bae
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.30 no.7
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    • pp.144-149
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    • 2002
  • This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.

Design and Dynamic Walking Simulation of a Biped Robot (이족보행로봇의 설계와 동적보행을 위한 모의실험)

  • Park, In-GYu;Youm, Young-Il
    • Proceedings of the KIEE Conference
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    • 2001.11c
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    • pp.87-90
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    • 2001
  • This paper presents a design of new type biped robot and dynamic walking simulation for this system. The robot is distinguished from other one by which has a parallel mechanism type trunk and lead-screw type actuators to drive the joints of the trunk, knee and ankle. The basic consideration on the design is that it is able to accommodate itself to human's daily environments without any other modification of around and also to operate its upper limbs more smoothly with a spine functional trunk. It is designed according to a human with about 130 cm height and about 30 kg weight. And it also is able to dynamically walk on an even ground. It has constructed with total 14 DOFs which have two legs, a hip, and a trunk. The joints of each leg and trunk are adopted with a parallel structure which has good kinematic characteristics and take light weight. To test of the capacity of joint actuators and to analysis of the dynamic properties of the biped robot, optimized trunk trajectory is determined by means of an approximated FFT method based on ZMP criteria, and dynamic simulation is performed using DADS with a 1.1 time/step velocity on the even ground during four steps.

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Exploiting Implicit Parallelism for Single Loops in Java Programming Language (JAVA 프로그래밍 언어에서 단일루프구조의 무시적 병렬성 검출)

  • Kwon, Oh-Jin
    • Journal of Information Management
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    • v.29 no.3
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    • pp.1-26
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    • 1998
  • The loop is a fundamental for the parallelism exploiting as it has a large portion of execution time for sequential Java program on the parallel machine. This paper proposes the method of exploiting the implicit parallelism through the analysis of data dependence in the existing Java programming language having a single loop structure. The parallel code generation method through the restructuring compiler and the translation method of Java source program into multithread statement, which is supported in the level of the Java programming language, are also proposed here. The performance test of the program translated into the thread statement is conducted using the trip count of loop and the thread count as parameters. The restructuring compiler makes it possible for users to reduce overhead and exploit parallelism efficiently in the Java programming.

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Cleavage Fracture Phenomenon in Silicon Chips with Wafer Grinding-Induced Scratch Marks (웨이퍼 그라인딩 공정으로 생성된 스크래치 마크를 갖는 실리콘 칩들에서의 벽개 파괴현상)

  • Lee, Dong-Ki;Lee, Tea-Gyu;Lee, Seong-Min
    • Korean Journal of Metals and Materials
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    • v.49 no.9
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    • pp.726-731
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    • 2011
  • The present work shows how the flexural displacement-induced fracture strength of silicon devices, whose back surfaces have wafer grinding-induced scratch marks, depends on the crystallographic orientation. Experimental results indicate that silicon devices with scratch marks parallel to their lateral direction (i.e. reference axis in this work) are very susceptible to flexural fracture, as compared to devices with marks which deviated from the direction. The 3-point bending test shows that the fracture strength of silicon devices having marks which are oriented away from the reference axis is 2.6 times higher than that of devices with marks parallel to the axis. It was particularly interesting to see that silicon devices with identical preferred marks even reveal different fracture strengths, depending on whether the marks are involved in specific crystal planes such as {111} or {011}, called cleavage planes. This work demonstrates that silicon devices with the reference axis-aligned scratch marks not existing on such cleavage planes can have higher fracture strength approximately 20% higher than those existing on the planes.

Design and evaluation of binocular type six-component load cell by using experimental technique (실험계획법을 이용한 쌍안경식 6축 로드셀의 설계 및 상호간섭 오차 평가)

  • Kang, Dae-Im;Kim, Gab-Sun;Jeong, Su-Yeon;Joo, Jin-Won
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.21 no.11
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    • pp.1921-1930
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    • 1997
  • This paper presents the effective technique to design a six-axis load cell by using experimental design with an orthogonal array. A binocular structure is used as a basic sensing element for a load cell instead of the parallel plate structure. The finite element method is adopted to obtain strain distributions of the sensing element, and by doing the analysis of variances, its results are utilized in determining the factor which is more influential to the output strain. Calibration test results show that the developed six-axis loa cell with the maximum capacities of 196 N in forces and 19.6 N. m in moments is evaluated to be useful with the coupling error less than 2.5%.

Effect of Design Shape on Fatigue Life of Plug Welded Joint (플러그 용접이음부의 피로수명에 미치는 설계형상의 영향)

  • 임재규;이중삼;서도원
    • Journal of Welding and Joining
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    • v.17 no.2
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    • pp.29-35
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    • 1999
  • This study was intended to use for the fatigue test in real structures and offer basic data for optimum welding structure design. To this purpose, we obserded the effect of the size and distance of plug welding hole on the static strength and fatigue life of welding structure under the shear/bending load for the improvement of fatigue life of plug welding joint between S/MBR and C/MBR in the lower structure of large bus. The result below is shown through this study. 1) Static and fatigue strength are strongly influenced by the direction of plug weld hole distributed. 2) Distances and diameters of the distributed holes are little dependent on the static strengths 3) In case of the directions of the distributed plug weld holes are vertical to the loading pin, fatigue life is dependent on distance of the distributed hole. 4) In case of the directions of the distributed plug weld holes are parallel to the loading pin, fatigue life is dependent on distance of the hole diameter.

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