• 대한산업공학회지
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• 제29권1호
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• pp.49-64
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• 2003

Although assembly sequence planning is an essential task in assembly process planning, it is known as one of the most difficult and time consuming jobs because its complexity is increased geometrically when the number of parts in an assembly is increased. The purpose of this study is to develop a more efficient algorithm for generating assembly sequences automatically. By considering subassemblies, a new heuristic method generates a preferred parallel assembly sequence that can be used in robotic assembly systems. A parallel assembly sequence concept provides a new representation scheme for an assembly in which the assembly sequence precedence information is not required. After an user inputs both the directional mating relation information and the mating condition information, an assembly product is divided into subgroups if the product has cut-vertices. Then, a virtual disassembly process is executed to generate alternate parallel assembly sequences with intermediate assembly stability. Through searching parts relations in the virtual disassembly process, stable subassemblies are extracted from translation-free parts along disassembling directions and this extraction continues until no more subassemblies are existed. Also, the arithmetic mean parallelism formula as a preference criterion is adapted to select the best parallel assembly sequence among others. Finally a preferred parallel assembly sequence is converted to an assembly BOM structure. The results from this study can be utilized for developing CAAPP(Computer-Aided Assembly Process Planning) systems as an efficient assembly sequence planning algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• 한국지능시스템학회논문지
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• 제18권3호
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• pp.323-328
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• 2008

본 논문에서는 연산 중심의 DSP 작업에 대한 성능을 유지하면서 제어 작업을 효과적으로 수행할 수 있는 프로세서 구조를 제안하고 구현하였다. 전통적으로 DSP작업은 직렬 연결된 연산기로 구현되지만, 제안한 프로세서에서는 곱셈기, 2개의 ALU, 읽기/쓰기 유닛 등 4개의 실행 유닛이 병렬로 배치되어 있고 수퍼스칼라 방식으로 제어되므로 동시에 처리된다. 제안된 프로세서를 사용하여 AC-3 오디오 복호화기를 구현하여 성능이 37.8% 향상됨을 확인하였다. 이와 같은 연구는 기존의 고성능 DSP를 사용할 수 없는 저가격의 가전기기용 부품제작에 활용이 가능하다.

• 수면정신생리
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• 제5권1호
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• pp.12-17
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• 1998

Circadian rhythms in subjective alertness, mood, and performance can be classified as psychological rhythm, compared with physiological rhythm such as body temperature and hormonal change. While in normal condition entrained by 24hr zeitgeber, subjective alertness would reach its maximum value around midday, subjective alertness would parallel body temperature rhythm with its peak at evening in non-entrained, free-running state. With desynchronization technique, subjective alertness rhythm is thought to be controlled by both temperature and sleep-wake rhythm oscillator. Circadian performance rhythms depend on the kind of task tested. It shows parallelism with body temperature rhythm when subjects are tested with simple, repetitive task. But when tested with tasks requiring complex verbal reasoning or immediate memory, subjects would perform them best at early morning, with performance decreasing as time of day advances. The desynchronization technique shows that circadian performance rhythm of simple, repetitive task is dependent on temperature oscillator but circadian performance rhythm of complex verbal reasoning is influenced by both temperature and sleep-wake rhythm oscillator or another independent oscillator. It would be worthwhile to compare psychological rhythm with hormonal change such as cortisol and melatonin. And more simple and time-saving method than desynchronization technique may facilitate the study of the mechanism underlying psychological rhythm.

• 한국경영과학회지
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• 제23권2호
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• pp.15-27
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• 1998

In the parallel processing systems, a compiler partitions a loaded program into tasks, allocates the tasks on multiple processors and schedules the tasks on each allocated processor. In this paper we suggest a Genetic Algorithm(GA) based scheduling method to find an optimal allocation and sequence of tasks on each Processor. The suggested method uses a chromosome which consists of task sequence and binary string that represent the number and order of tasks on each processor respectively. Two correction algorithms are used to maintain precedency constraints of the tasks in the chromosome. This scheduling method determines the optimal number of processors within limited numbers, and then finds the optimal schedule for each processor. A result from computational experiment of the suggested method is given.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2018년도 춘계학술발표대회
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• pp.469-470
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• 2018

Object tracking is a common task in computer vision, an essential part of various vision-based applications. After several years of development, object tracking in video is still a challenging problem because of various visual properties of objects and surrounding environment. Particle filter is a well-known technique among common approaches, has been proven its effectiveness in dealing with difficulties in object tracking. However, particle filter is a high-complexity algorithms, which is an severe disadvantage because object tracking algorithms are required to run in real time. In this research, we utilize parallel programming to accelerate particle filter-based object tracking algorithms. Experimental results showed that our approach reduced the execution time significantly.

• 한국항공우주학회지
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• 제42권5호
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• pp.361-367
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• 2014

본 논문은 최근에 널리 사용되는 다중코어 컴퓨팅 환경에서 병렬 다중프론트 해법의 스케쥴링 및 부하조절 기법에 대해 논의한다. 통상적으로 구조해석 문제들은 불규칙한 격자계와 혼재된 물성 때문에 병렬화 알고리즘 구현 시 병목현상을 일으키고 불필요한 유휴시간을 초래한다. 따라서 이를 극복하며 효율성을 향상시키기 위해 다중쓰레드 기반 환경에 걸맞는 작업 스케쥴링 및 부하 분산 기법의 적용이 필수적이다. 본 논문에서 제시된 정적, 동적 스케줄링 기법과 정적 전 임무 분산, 최소최대 임무 결합 등의 부하 분산 기법들에 대한 이론적, 실제 결과를 제시함으로서 그 유용성을 논의하고자 한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권6호
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• pp.2648-2668
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• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

• 대한임베디드공학회논문지
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• 제11권6호
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• pp.325-334
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• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• 한국정보처리학회논문지
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• 제6권8호
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• pp.2050-2059
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• 1999

다중 처리기 시스템에서의 병렬 처리를 위한 스케줄링 문제는 지난 수 십년 동안 중요한 연구 과제가 되어왔다. 다중 처리기 스케줄링 문제(multiprocessor scheduling problem)란 다중 처리기 시스템에서 병렬 수행 시간(parallel execution time)을 최소화 할 수 있는 최적의 스케줄을 구하는 문제로 정의된다. 복제 중심 타스크 스케줄링은 이러한 문제를 풀기 위한 비교적 새로운 접근 방법이다. 이 논문은 복제 중심 스케줄링 알고리즘들을 타스크 복제 방법에 따라서 전체 복제와 부분 복제의 두 가지로 분류하고, 그 두가지 방법의 장점들을 결합한 새로운 스케줄링 알고리즘을 제안한다. 시뮬레이션 결과는 이 논문에서 제안된 스케줄링 알고리즘이 비슷한 복잡도(time complexity)를 갖는 다른 스케줄링 알고리즘보다 우수함을 보여준다.