• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.5
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• pp.70-78
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• 2001

We have developed a novel driving system of 5' true color FED using voltage controlled PWM method which has current control effect. The proposed method has the advantage of voltage controlled pulse width modulation method and current control method. Also, we propose a new circuit model of FED subpixel for circuit simulation of FED driving circuits, considering some parasitic effects, i.e., cross talk, line coupling effect and leakage current to the adjacent cathode lines. Output stage of the data driving circuit is optimized using the proposed circuit model. In video data processing, FED controller uses the parallel processing of R.G.B input data, so duty ratio is maximized and brightness of FED increases. With this results, no noise and high quality performance is achieved in display of 5' true color FED.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.2
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• pp.1-10
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• 2010

Mapping virtual process topology to physical processor topology is one of the most important design issues in parallel programming. However, the mapping problem is complicated due to the topology irregularity and routing complexity. This paper proposes a new process mapping scheme called adjacency-based mapping (AM) for irregular cluster systems assuming that the two-dimensional mesh process topology is specified as an interprocess communication pattern. The cluster systems have been studied and developed for many years since they provide high interconnection flexibility, scalability, and expandability which are not attainable in traditional regular networks. The proposed AM tries to map neighboring processes in virtual process topology to adjacent processors in physical processor topology. Simulation study shows that the proposed AM results in better mapping quality and shorter interprocess latency compared to the conventional approaches.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.27 no.6
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• pp.293-299
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• 2015

In Korea, it is the law that an apartment building which consists of over 100 households must have a ventilation system installed, either natural or mechanical. The heat recovery ventilator (HRV) is great way to reduce energy consumption. In this research we confirmed that based on site's construction plan and existing diffuser form, performed purpose CFD which simulates operation in temperatures below $-5^{\circ}C$ to circumstances of installation of an HRV in an apartment. As a result of this research we found that when the diffuser's aperture area was adjusted, the distribution of air temperature and residence time of air was more equally distributed and air temperature was higher, compared to when the diffuser has an identical aperture area. We also found that we are able to increase even more air temperature and air distribution of air temperature and residence time of air was even more equally distributed when run in parallel with a splitter damper.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.3
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• pp.47-61
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• 2012

parallel transmitting system with channel bonding method have been proposed to transmit mass content such as UHD(Ultra High Definition) in HFC(Hybrid Fiber Coaxial) networks. However, this system may lead to channel resource problem because the system needs many channels to transmit mass content. In this paper, we analyze three effective bandwidth approximation algorithms to use the bonding channel efficiently. These algorithms are the effective bandwidth of Gaussian approximation method algorithm proposed by Guerin, the effective bandwidth based on statistics of video frames proposed by Lee and the effective bandwidth based on Gaussian traffic proposed by Nagarajan. We also evaluate compatibility of algorithms to the mass broadcasting service. OPNET simulator is used to evaluate the performance of the algorithms. For accuracy of simulation, we make mass source from real HD broadcasting stream.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
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• 2007.11a
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• pp.193-198
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• 2007

KIER has been developing the anode supported flat tubular SOFC stack for the intermediate temperature $(700{\sim}800^{\circ}C)$ operation. for this purpose, we have first fabricated anode supported flat tubular cells by the optimization between the current collecting method and the induction brazing process. After that we designed the compact fuel & air manifold by adopting the simulation technique to uniformly supply fuel & air gas and the unique seal & insulation method to make the more compact stack. For making stack, the prepared anode-supported flat tubular cells with effective electrode area of $90cm^2$ of connected in series with 12 modules, in which one module consists of two cells connected in parallel. The performance of stack in 3 % humidified $H_2$ and air at $800^{\circ}C$ shows maximum power of 507 W. Through these experiments, we obtained basic & advanced technology of the anode-supported flat tubular cell and established the proprietary concept of the anode-supported flat tubular SOFC stack in KIER.

• Journal of Sensor Science and Technology
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• v.19 no.2
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• pp.99-111
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• 2010

This paper proposes an efficient hardware architecture to estimate disparities between 2D images for generating 3D depth images in a stereo vision system. Stereo matching methods are classified into global and local methods. The local matching method uses the cost functions based on pixel windows such as SAD(sum of absolute difference), SSD(sum of squared difference) and NCC(normalized cross correlation). The NCC-based cost function is less susceptible to differences in noise and lighting condition between left and right images than the subtraction-based functions such as SAD and SSD, and for this reason, the NCC is preferred to the other functions. However, software-based implementations are not adequate for the NCC-based real-time stereo matching, due to its numerous complex operations. Therefore, we propose a fast pipelined hardware architecture suitable for real-time operations of the NCC function. By adopting a block-based box-filtering scheme to perform NCC operations in parallel, the proposed architecture improves processing speed compared with the previous researches. In this architecture, it takes almost the same number of cycles to process all the pixels, irrespective of the window size. Also, the simulation results show that its disparity estimation has low error rate.