• Title/Summary/Keyword: Parallel Simulation

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Design of 2nd-harmonic Quadrature Mixer for Ultra Wideband(UWB) Systems (2차 고조파를 이용한 UWB 시스템용 쿼드러쳐 혼합기 설계)

  • Jung, Goo-Young;Lim, Jong-Hyuk;Choi, Byung-Hyun;Yun, Tae-Yeoul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.12 s.115
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    • pp.1156-1163
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    • 2006
  • This paper presents an ultra wideband(UWB) direct conversion mixer for IEEE 802.15.3a applications with simulation and measurement results. Since the direct conversion mixing causes dc-offset and even-order distortion, the proposed mixer adopts an anti-parallel diode pairs(APDPs) to solve these problems. The proposed mixer consists of an in-phase wilkinson power divider over $3.1{\sim}4.8GHz$, a wideband $45^{\circ}$ power divider over $1.5{\sim}2.4GHz$, and miniatured band pass filters(BPFs) for RF-LO isolations. The conversion loss is optimized with impedance matchings between APDPs and wideband components. The measured mixer shows the conversion loss of 13.5 dB, input third-order intercept-point($IIP_3$) of 7 dBm, and 1-dB gam compression point($P_{1dB}$) of -4 dBm. Quadrature(I/Q) outputs have the magnitude difference of about 1 dB and phase difference of ${\pm}3^{\circ}$.

Cortical Thickness Estimation Using DIR Imaging with GRAPPA Factor 2 (DIR 영상을 이용한 피질두께 측정: GRAPPA 인자 2를 이용한 비교)

  • Choi, Na-Rae;Nam, Yoon-Ho;Kim, Dong-Hyun
    • Investigative Magnetic Resonance Imaging
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    • v.14 no.1
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    • pp.56-63
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    • 2010
  • Purpose : DIR image is relatively free from susceptibility artifacts therefore, DIR image can make it possible to reliably measure cortical thickness/volume. One drawback of the DIR acquisition is the long scan time to acquire the fully sampled 3D data set. To solve this problem, we applied a parallel imaging method (GRAPPA) and verify the reliability of using the volumetric study. Materials and methods : Six healthy volunteers (3 males and 3 females; age $25.33{\pm}2.25$ years) underwent MRI using the 3D DIR sequence at a 3.0T Siemens Tim Trio MRI scanner. GRAPPA simulation was performed from the fully sampled data set for reduction factor 2. Data reconstruction was performed using MATLAB R2009b. Freesurfer v.4.3.0 was used to evaluate the cortical thickness of the entire brain, and to extract white matter information from the DIR image, Analyze 9.0 was used. The global cortical thickness estimated from the reconstructed image was compared with reference image by using a T-test in SPSS. Results : Although reduced SNR and blurring are observed from the reconstructed image, in terms of segmentation the effect was not so significant. The volumetric result was validated that there were no significant differences in many cortical regions. Conclusion : This study was performed with DIR image for a volumetric MRI study. To solve the long scan time of 3D DIR imaging, we applied GRAPPA algorithm. According to the results, fast imaging can be done with reduction factor 2 with little loss of image quality at 3.0T.

Splitting of Surface Plasmon Resonance Peaks Under TE- and TM-polarized Illumination

  • Yoon, Su-Jin;Hwang, Jeongwoo;Lee, Myeong-Ju;Kang, Sang-Woo;Kim, Jong-Su;Ku, Zahyun;Urbas, Augustine;Lee, Sang Jun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.296-296
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    • 2014
  • We investigate experimentally and theoretically the splitting of surface plasmon (SP) resonance peaks under TE- and TM-polarized illumination. The SP structure at infrared wavelength is fabricated with a 2-dimensional square periodic array of circular holes penetrating through Au (gold) film. In brief, the processing steps to fabricate the SP structure are as follows. (i) A standard optical lithography was performed to produce to a periodic array of photoresist (PR) circular cylinders. (ii) After the PR pattern, e-beam evaporation was used to deposit a 50-nm thick layer of Au. (iii) A lift-off processing with acetone to remove the PR layer, leading to final structure (pitch, $p=2.2{\mu}m$; aperture size, $d=1.1{\mu}m$) as shown in Fig. 1(a). The transmission is measured using a Nicolet Fourier-transform infrared spectroscopy (FTIR) at the incident angle from $0^{\circ}$ to $36^{\circ}$ with a step of $4^{\circ}$ both in TE and TM polarization. Measured first and second order SP resonances at interface between Au and GaAs exhibit the splitting into two branches under TM-polarized light as shown in Fig. 1(b). However, as the incidence angle under TE polarization is increased, the $1^{st}$ order SP resonance peak blue-shifts slightly while the splitting of $2^{nd}$ order SP resonance peak tends to be larger (not shown here). For the purpose of understanding our experimental results qualitatively, SP resonance peak wavelengths can be calculated from momentum matching condition (black circle depicted in Fig. 2(b)), $k_{sp}=k_{\parallel}{\pm}iG_x{\pm}jG_y$, where $k_{sp}$ is the SP wavevector, $k_{\parallel}$ is the in-plane component of incident light wavevector, i and j are SP coupling order, and G is the grating momentum wavevector. Moreover, for better understanding we performed 3D full field electromagnetic simulations of SP structure using a finite integration technique (CST Microwave Studio). Fig. 1(b) shows an excellent agreement between the experimental, calculated and CST-simulated splitting of SP resonance peaks with various incidence angles under TM-polarized illumination (TE results are not shown here). The simulated z-component electric field (Ez) distribution at incident angle, $4^{\circ}$ and $16^{\circ}$ under TM polarization and at the corresponding SP resonance wavelength is shown in Fig. 1(c). The analysis and comparison of theoretical results with experiment indicates a good agreement of the splitting behavior of the surface plasmon resonance modes at oblique incidence both in TE and TM polarization.

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Assessing Estimation Methods of the Expected Crashes using Panel Traffic Crash Data (패널교통사고자료 기반 기대교통사고건수 추정기법 평가)

  • Sin, Gang-Won
    • Journal of Korean Society of Transportation
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    • v.29 no.1
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    • pp.103-111
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    • 2011
  • To evaluate highway safety countermeasures or identify high risk sites, the expected crashes for a site (or segment) have been estimated using the panel crash data. Past studies show that two different methods can be employed to estimate the expected crashes: observed crash based method and empirical Bayes (EB) method. This study conducts a simulation study to analyze how the estimation errors of the two estimates are affected by the different structures of the panel crash data and the presence of the change in safety over time. The results disclose that the estimation errors of the observed crash based estimates (i.e. the mean observed crash and comparative parallel estimate) are always greater than those of the EB estimates regardless of the structure of the panel crash data and the presence of the change in safety over time. Thus, it is highly recommended that the EB method be used in the study of traffic safety to obtain more reliable estimates for the expected crashes. In addition, this study corroborates that the estimation errors of the two estimates decrease as the analysis periods increase if safety does not change over time. Hence, it is also recommended that the 1-year analysis period used for identifying high risk sites in Korea be extended to produce more efficient estimates of the time-constant expected crashes.

Comparison of Monitor Units Obtained from Measurements and ADAC Planning System for High Energy Electrons (측정과 ADAC 치료계획 시스템에서 계산된 고에너지 전자선의 Monitor Unit Value 비교)

  • Lee, Re-Na;Choi, Jin-Ho;Suh, Hyun-Suk
    • Progress in Medical Physics
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    • v.13 no.4
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    • pp.202-208
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    • 2002
  • The purpose of this study is to evaluate the monitor unit obtained from various methods for the treatment of superficial cancers using electron beams. Thirty-three breast cancer patients who were treated in our institution with 6, 9, and 12 MeV electron beams, were selected for this study. For each patient, irregularly shaped treatment blocks were drawn on simulation film and constructed. Using the irregular blocks, monitor units to deliver 100 cGy to the dose maximum (dmax) were calculated from measurement and three-dimensional radiation treatment planning (3D RTP) system (PINNACLE 6.0, ADAC Laboratories, Milpitas CA) Measurements were made in solid water phantom with plane parallel (PP) chamber (Roos, OTW Germany) at 100 cm source-to surface distances. CT data was used to investigate the effect of heterogeneity. Monitor units were calculated by overriding CT values with 1 g/㎤ and in the presence of heterogeneity. The monitor unit values obtained by the above methods were compared. The dose, obtained from measurement in solid water phantom was higher than that of RTP values for irregularly shaped blocks. The maximum differences between monitor unit calculated in flat water phantom at gantry zero position were 4% for 6 MeV and 2% for 9 and 12 MeV electrons. When CT data was used at a various gantry angle the agreement between the TPS data with and without density correction was within 3% for all energies. These results indicate that there are no significant difference in terms of monitor unit when density is corrected for the treatment of breast cancer patients with electrons.

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Performance Improvement of Asunchronous DS-CDMA Systems with a Multistage Interference Canceller in the Presence of Timing and Phase Errors (칩 동기 에러와 위상 에러가 존재하는 환경에서 다단 간섭제거기에 의한 비동기 DS-CDMA 시스템의 성능 개선)

  • 김봉철;강근정;오창헌;조성준
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.1
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    • pp.1-10
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    • 2001
  • In this paper, a multistage parallel interference canceller (MPIC) and a partial multistage parallel interference canceller (PMPIC) are employed as a technique for improving the performance of the asynchronous DS-CDMA systems. The degree of the effect of the timing errors and phase errors on the interference cancellation capability of two types of cancellers is theoretically analyzed and the computer simulation is performed to confirm the analytical results. From the results, the large performance improvement is obtained by employing MPIC and PMPIC with perfect synchronization over the conventional matched filter, and the performance improvement obtained by MPIC and PMPIC is very close to each other as the number of the stage of MPIC and PMPIC increases. When the timing errors and phase errors are considered (in the case of imperfect synchronization), the performance improvement reduces as the performance degradation at the first stage (no cancellation) has a bad effect on the decision statistics at each stage. However MPIC and PMPIC have the strong interference cancellation capability in spite of imperfect synchronization as the number of the stage increases. An interference canceller, which has the strong interference cancellation capability as well as lower complexity for the implementation, is needed for practical systems with timing errors and phase errors because the perfect synchronization is impossible. Therefore, the excellent tradeoff between complexity and performance offered by PMPIC makes it an attractive approach for practical systems.

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The Motion Estimator Implementation with Efficient Structure for Full Search Algorithm of Variable Block Size (다양한 블록 크기의 전역 탐색 알고리즘을 위한 효율적인 구조를 갖는 움직임 추정기 설계)

  • Hwang, Jong-Hee;Choe, Yoon-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.66-76
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    • 2009
  • The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

Study of an In-order SMT Architecture and Grouping Schemes

  • Moon, Byung-In;Kim, Moon-Gyung;Hong, In-Pyo;Kim, Ki-Chang;Lee, Yong-Surk
    • International Journal of Control, Automation, and Systems
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    • v.1 no.3
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    • pp.339-350
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    • 2003
  • In this paper, we propose a simultaneous multithreading (SMT) architecture that improves instruction throughput by exploiting instruction level parallelism (ILP) and thread level parallelism (TLP). The proposed architecture issues and completes instructions belonging to the same thread in exact program order. The issue and completion policy greatly reduces the design complexity and hardware cost of our architecture, compared with others that employ out-of-order issue and completion. On the other hand, when the instructions belong to different threads, the issue and completion orders for those instructions may not necessarily be identical to the fetch order. The processor issues instructions simultaneously from multiple threads to functional units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably improves performance and resource utilization with minimal additional hardware cost over the conventional superscalar processors. This paper proposes an SMT architecture with grouping as well as one without grouping. Without grouping, all threads dynamically and flexibly share most resources. On the other hand, in the SMT architecture with grouping, in which resources and threads are divided into several groups for design simplification, resources are shared only among threads belonging to the same group as those resources. Simulation results show that our processors with four and eight threads improve performance by three or more times over the conventional superscalar processor with comparable execution resources and policies, and that reasonable grouping reduces the design complexity of SMT processors with little negative effect on performance.

Efficient Symbol Detection Algorithm for Space-frequency OFDM Transmit Diversity Scheme (공간-주파수 OFDM 전송 다이버시티 기법을 위한 효율적인 심볼 검출 알고리즘)

  • Jung Yun ho;Kim Jae seok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.4C
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    • pp.283-289
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    • 2005
  • In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

Design of a 2.4GHz CMOS Low Noise Amplifier (2.4GHz CMOS 저잡음 증폭기)

  • 최혁환;오현숙;김성우;임채성;권태하
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.1
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    • pp.106-113
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    • 2003
  • In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.