• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.201-205
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• 1998

In this paper, the charge control with the input voltage feed forward is proposed for the input series-output parallel connected converter configuration for high voltage power conversion applications. This control scheme accomplishes the output current sharing for the output-parallel connected modules as well as the input voltage sharing for the input-series connected modules for all operating conditions including the transients. It also offers the robustness for the component value mismatches among the modules.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.17-27
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• 2005

In this paper, we introduce a Parallel Interference Canceller (PIC) based sorting method to improve performance in the MC-DS/CDMA environment. A conventional PIC estimates and subtracts out all of the MAI (Multiple Access Interference) for each user in parallel. The parallel process ensures the low delay for the detection of all users. Also this scheme requires more stages for having better performance. Since the performance of PIC is strongly related to the correct MAI estimation, we introduce the IC (Interference Cancellation) scheme to estimate the accurate weaker signal group than the desired signal using conventional PIC. The principle of the proposed receiver sorts in descending order by the strength of signal and subtracts the MAI of the strong interferers from the desired signal for the accurate estimate of the weaker signals. Following this, the proposed scheme cancels out the improved weaker interference from the desired signal, using the output of the pre-step. In this result, the proposed system obtains better BER performance than the conventional PIC because the accuracy of the strong signal is improved. However, a disadvantage exists in that the processing time has slightly longer delay than the PIC owing to the power sorting and the MAI estimation process. The system performance evaluates and compares other non-liner It according to the number of sub-carriers in the limited-bandwidth.

• Journal of Power Electronics
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• v.5 no.2
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• pp.160-165
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• 2005

In a parallel operation of UPS, there are two types of circulating currents between UPS. One is the low order circulating current with a fundamental frequency caused by the amplitude and phase differences of UPS output voltages, and the other is the harmonic circulating current with PWM switching frequency caused by non-synchronized PWM waveforms among UPS. The elimination of the low order circulating current is essential for optimal load sharing in parallel operations of UPS, which can be accomplished by the phase and magnitude control at each UPS. The harmonic circulating current may cause troubles and deteriorate in performance of the controller for optimal load sharing in parallel operation of UPS. This paper presents a PWM synchronizing method to eliminate the harmonic circulation current in parallel operation of UPS. The effectiveness of the proposed scheme has been investigated and verified through experiments by a 50kVA UPS.

• East Asian mathematical journal
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• v.14 no.1
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• pp.63-76
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• 1998

we consider the hp-version to solve non-constant coefficients elliptic equations $-div(a{\nabla}u)=f$ with Dirichlet boundary conditions on a bounded polygonal domain $\Omega$ in $R^2$. In [6], M. Suri obtained an optimal error-estimate for the hp-version: ${\parallel}u-u^h_p{\parallel}_{1,\Omega}{\leq}Cp^{(\sigma-1)}h^{min(p,\sigma-1)}{\parallel}u{\parallel}_{\sigma,\Omega}$. This optimal result follows under the assumption that all integrations are performed exactly. In practice, the integrals are seldom computed exactly. The numerical quadrature rule scheme is needed to compute the integrals in the variational formulation of the discrete problem. In this paper we consider a family $G_p=\{I_m\}$ of numerical quadrature rules satisfying certain properties, which can be used for calculating the integrals. Under the numerical quadrature rules we will give the variational form of our non-constant coefficients elliptic problem and derive an error estimate of ${\parallel}u-\tilde{u}^h_p{\parallel}_{1,\Omega}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.24-37
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• 2024

To address the requirement for high-speed encryption of large amounts of data, this study improves the widely adopted cipher block chaining (CBC) mode and proposes a controllable parallel cipher block chaining (CPCBC) block cipher mode of operation. The mode consists of two phases: extension and parallel encryption. In the extension phase, the degree of parallelism n is determined as needed. In the parallel encryption phase, n cipher blocks generated in the expansion phase are used as the initialization vectors to open n parallel encryption chains for parallel encryption. The security analysis demonstrates that CPCBC mode can enhance the resistance to byte-flipping attacks and padding oracle attacks if parallelism n is kept secret. Security has been improved when compared to the traditional CBC mode. Performance analysis reveals that this scheme has an almost linear acceleration ratio in the case of encrypting a large amount of data. Compared with the conventional CBC mode, the encryption speed is significantly faster.

• Journal of KIISE
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• v.41 no.9
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• pp.686-698
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• 2014

Recently, large-scale streaming sensor data have emerged due to explosive supply of smart phones, diffusion of IoT and Cloud computing technology, and generalization of IoT devices. Also, researches on combination of semantic web technology are being actively pushed forward by increasing of requirements for creating new value of data through data sharing and mash-up in large-scale environments. However, we are faced with big issues due to large-scale and streaming data in the inference field for creating a new knowledge. For this reason, we propose the RDFS rule based parallel reasoning scheme to service by processing large-scale streaming sensor data with the semantic web technology. In the proposed scheme, we run in parallel each job of Rete network algorithm, the existing rule inference algorithm and sharing data using the HBase, a hadoop database, as a public storage. To achieve this, we implement our system and evaluate performance through the AWS data of the weather center as large-scale streaming sensor data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.2
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• pp.163-171
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• 2016

In order to detect the exact position of high-speed train, it is necessary to obtain location information from the transponder tag installed along the track. In this paper, we proposed parallel descrambling scheme for high-speed railway transponder system, which aims for reducing the processing time required to decode telegram. Since a telegram is stored in a tag after information bits are scrambled by an encoder, decoding procedure includes descrambling of received telegram to recover the original information bits. By analyzing the structure of the descrambling shift register circuit, we proposed a parallel descrambling scheme for fast decoding of telegram. By comparing the required number of clocks, it is shown that the proposed scheme significantly outperforms the original one.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.221-228
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• 2008

In the 2-phase excited BLDC motor drives using a unipolar PWM scheme, there exists, in some cases, a unwanted leakage current which flows through the anti -parallel diode in the non-excited phase leg of the inverter. In this paper the cases in which the leakage current exists and the influence of the leakage current are analyzed, and a novel unipolar PWM scheme which can eliminate the leakage current is proposed. The leakage current increases as the motor speed is increased or PWM duty is decreased, and as a result the output power of the motor is reduced considerably. The effectiveness of the proposed unipolar PWM scheme isverified through the comparative simulations and experiments.