• 제목/요약/키워드: Parallel Processing System

검색결과 888건 처리시간 0.028초

동기페이저측정기를 활용한 전력계통 상태벡터 결정을 위한 병렬처리기법 (Parallel Processing Techniques to Determine State Vectors of a Power System using PMU)

  • 이기송;이찬주;조기선;신중린
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 A
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    • pp.72-74
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    • 2000
  • This paper presents the linear model of the measurement system with Phasor Measurement Units (PMU's) and the parallel processing technique to determinate state vectors of a power system. The conventional model of the PMU measurement system is in a dilemma that it is not applicable to optimal PMU placements and it needs more PMU to apply this model. In order to improve this defect, in this paper, the extended linear model which adaptable to optimal PMU placements considering the feature of zero injection bus is proposed. Because the proposed model is expressed as over-determined measurement equation, the efficient algorithm is needed. This paper proposed the partitioning scheme and the process algorithm for parallel determinating state vectors of a power system efficiently. The performance of the proposed linear model and the parallel processing algorithm is evaluated with IEEE sample systems.

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철도에서 병렬 순환 잉여 기법을 이용한 차세대 무선인식 시스템에 관한 연구 (A Study on the Advanced RFID System in Railway using the Parallel CRC Technique)

  • 강태규;이재호;신석균;이재훈;이기서
    • 한국철도학회논문집
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    • 제8권1호
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    • pp.1-5
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    • 2005
  • This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15% In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

트리거 처리 4 단계 일관성 레벨 (Four Consistency Levels in Trigger Processing)

  • 박종범
    • 한국정보과학회논문지:데이타베이스
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    • 제29권6호
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    • pp.492-501
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    • 2002
  • 비동기 트리거 처리기(ATP)는 데이타베이스 트랜잭션의 수행이 완료된 후에 트리거를 처리하는 소프트웨어 시스템이다. ATP 내에서는 트리거 조건의 효율적인 검사를 위하여 차별화 네트워크(discrimination network)가 사용된다. 차별화 네트워크는 내부 상태를 메모리 노드에 저장한다. TrigerMan은 하나의 ATP로써 차별화 네트워크로써 Gator 네트워크를 사용한다. 데이타베이스의 내용 변화는 트리거맨에 토큰 형태로 전달된다. 트리거 조건의 검사는 토큰이 Gator 네트워크를 통과하면서 이루어지는데, 이때 Gator 네트워크의 메모리 노드들이 갱신된다. 토큰의 병렬처리는 시스템의 성능을 향상시키는 여러 방법 중 하나이지만 통제되지 않은 병렬처리는 잘못된 트리거 액션 수행을 유발한다. 이 논문은, 최소한의 이상 현상만을 허용하며 토큰의 병렬 처리를 가능하게 하는, 네 가지 트리거 처리 일관성 레벨을 제안한다. 우리는 각 일관성 레벨에 대하여 병렬 토큰 처리를 가능하게 하는 고유한 기술을 개발하였다. 제안된 기술은 안정된 방법이라는 사실이 공리를 통하여 증명되었으며, 이 기술은 실체화 된 (materialized) 뷰 유지 (view maintenance)에 사용될 수 있다.

계층화 모션 추정법과 병렬처리를 이용한 차량 움직임 측정 알고리즘 개발 및 구현 (Design and Implementation of Algorithms for the Motion Detection of Vehicles using Hierarchical Motion Estimation and Parallel Processing)

  • 강경훈;정성태;이상설;남궁문
    • 한국멀티미디어학회논문지
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    • 제6권7호
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    • pp.1189-1199
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    • 2003
  • 본 논문에서는 계층화 모션 추정법과 병렬 처리를 이용한 차량의 움직임 측정 알고리즘을 제안한다. 본 시스템에서는 CMOS 센서를 통하여 도로 영상을 캡쳐한다. 그 다음에 영상을 작은 블록들로 나누고 블록매칭을 이용하여 각 블록의 움직임을 계산한다. 그리고 움직임이 비슷한 블록들을 클러스터링하여 차량의 움직임을 측정한다. 본 논문에서는 실시간 동작을 위하여 계층화 모션 추정법과 병렬 처리에 의거한 블록매칭 알고리즘을 제안한다. 병렬처리를 위해서는 파이프라인과 데이터 플로우 기법을 도입하였다. 본 논문에서 제안된 시스템은 기존의 내장형 시스템을 이용하여 구현되었다. 제안된 블록매칭 알고리즘은 PLD(Programmable Logic Device)를 이용하여 구현하였고 클러스터링 알고리즘은 ARM 프로세서를 이용하여 구현하였다. 실험 결과에 의하면 본 논문에서 구현된 시스템은 차량의 움직임을 실시간으로 추출할 수 있었다.

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Parallel Fuzzy Inference Method for Large Volumes of Satellite Images

  • Lee, Sang-Gu
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제1권1호
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    • pp.119-124
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    • 2001
  • In this pattern recognition on the large volumes of remote sensing satellite images, the inference time is much increased. In the case of the remote sensing data [5] having 4 wavebands, the 778 training patterns are learned. Each land cover pattern is classified by using 159, 900 patterns including the trained patterns. For the fuzzy classification, the 778 fuzzy rules are generated. Each fuzzy rule has 4 fuzzy variables in the condition part. Therefore, high performance parallel fuzzy inference system is needed. In this paper, we propose a novel parallel fuzzy inference system on T3E parallel computer. In this, fuzzy rules are distributed and executed simultaneously. The ONE_To_ALL algorithm is used to broadcast the fuzzy input to the all nodes. The results of the MIN/MAX operations are transferred to the output processor by the ALL_TO_ONE algorithm. By parallel processing of the fuzzy rules, the parallel fuzzy inference algorithm extracts match parallelism and achieves a good speed factor. This system can be used in a large expert system that ha many inference variables in the condition and the consequent part.

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병렬처리를 이용한 화력발전소의 실시간 시뮬레이션 (Real time simulation using multiple DSPs for fossil power plants)

  • 박희준;김병국
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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    • pp.480-483
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    • 1997
  • A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed to develope real-time simulators. Vital points of real-time simulators are accuracy, computing speed, and deadline observing. In this paper, we present a enhanced strategy in which we can provide powerful computing power by parallel processing of DSP processors with communication links. We designed general purpose DSP modules, and a VME interface module. Because the DSP module is designed for general purpose, we can easily expand the parallel system by just connecting new DSP modules to the system. Additionally we propose methods about downloading programs, initial data to each DSP module via VME bus, DPRAM and processing sequences about computing and updating values between DSP modules and CPU30 board when the simulator is working.

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An Efficient String Matching Algorithm Using Bidirectional and Parallel Processing Structure for Intrusion Detection System

  • Chang, Gwo-Ching;Lin, Yue-Der
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제4권5호
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    • pp.956-967
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    • 2010
  • Rapid growth of internet applications has increased the importance of intrusion detection system (IDS) performance. String matching is the most computation-consuming task in IDS. In this paper, a new algorithm for multiple string matching is proposed. This proposed algorithm is based on the canonical Aho-Corasick algorithm and it utilizes a bidirectional and parallel processing structure to accelerate the matching speed. The proposed string matching algorithm was implemented and patched into Snort for experimental evaluation. Comparing with the canonical Aho-Corasick algorithm, the proposed algorithm has gained much improvement on the matching speed, especially in detecting multiple keywords within a long input text string.

로컬 버퍼 최적화를 통한 병렬 처리 캐니 경계선 검출기의 FPGA 설계 (FPGA Design of a Parallel Canny Edge Detector with Optimized Local Buffers)

  • 민인기;심수현;황승원;김선희
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.59-65
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    • 2023
  • Edge detection in image processing and computer vision is one of the most fundamental operations. Canny edge detection algorithm has excellent performance and is currently widely used. However, it is difficult to process the algorithm in real-time because the algorithm is complex. In this study, the equations required in the algorithm were simplified to facilitate hardware implementation, and the calculation speed was increased by using a parallel structure. In particular, the size and management of local buffers were selected in consideration of parallel processing and filter size so that data could be processed without bottlenecks. It was designed in verilog and implemented in FPGA to verify operation and performance.

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IoT/에지 컴퓨팅에서 저전력 메모리 아키텍처의 개선 연구 (A Study on Improvement of Low-power Memory Architecture in IoT/edge Computing)

  • 조두산
    • 한국산업융합학회 논문집
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    • 제24권1호
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    • pp.69-77
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    • 2021
  • The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

Simulation of Deformable Objects using GLSL 4.3

  • Sung, Nak-Jun;Hong, Min;Lee, Seung-Hyun;Choi, Yoo-Joo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제11권8호
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    • pp.4120-4132
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    • 2017
  • In this research, we implement a deformable object simulation system using OpenGL's shader language, GLSL4.3. Deformable object simulation is implemented by using volumetric mass-spring system suitable for real-time simulation among the methods of deformable object simulation. The compute shader in GLSL 4.3 which helps to access the GPU resources, is used to parallelize the operations of existing deformable object simulation systems. The proposed system is implemented using a compute shader for parallel processing and it includes a bounding box-based collision detection solution. In general, the collision detection is one of severe computing bottlenecks in simulation of multiple deformable objects. In order to validate an efficiency of the system, we performed the experiments using the 3D volumetric objects. We compared the performance of multiple deformable object simulations between CPU and GPU to analyze the effectiveness of parallel processing using GLSL. Moreover, we measured the computation time of bounding box-based collision detection to show that collision detection can be processed in real-time. The experiments using 3D volumetric models with 10K faces showed the GPU-based parallel simulation improves performance by 98% over the CPU-based simulation, and the overall steps including collision detection and rendering could be processed in real-time frame rate of 218.11 FPS.