• 전자공학회논문지B
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• 제28B권9호
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• pp.703-711
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• 1991

In this paper, an efficient storage reclamation algorithm for RISC parallel processing in the object orented programming environments is presented. The memory management for the dynamic memory allocation and the frequent memory access in object oriented programming is the main factor that decreases RISC parallel processing performance. The proposed algorithm can be efficiently allocated the memory space of RISCy computer which is required the frequent memory access, so it can be increased RISC parallel processing performance. The proposed algorithm is verified the efficiency by implementing C language on SUN SPARC(4.3 BSD UNIX).

• 대한전자공학회논문지SP
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• 제44권4호통권316호
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• pp.101-108
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• 2007

고성능 네트워크와 분산처리구조가 병렬처리와 함께 결합되면, 전체적인 디지털 신호처리 시스템의 계산능력, 신뢰도, 다양성을 향상시킨다. 본 논문에서는, 발전된 형태의 수중레이더 (sonar) 알고리즘인 수중정합장처리 (Matched-Field Processing MFP)를 위한 병렬처리 알고리즘을 디자인하고 다중 DSP 프로세서 기반의 병렬처리 시스템 상에서 성능분석과 함께 최적의 병렬처리 솔루션을 제안한다. 각각의 병렬 알고리즘은 특정한 도메인에서 주어진 계산량을 분산시키며 이를 통한 속도향상을 추구한다. 필요한 연산량과 형태에 따라서 병렬 알고리즘은 각기 다른 성능향상을 보여준다. 또한, 알고리즘의 계산량 분산방식 프로세서간의 통신방식, 알고리즘의 복잡도, 프로세서의 속도, 목적하는 시스템의 구성에 따라서 다양한 성능지표를 보여준다. 제안하는 주파수와 출력값 기반의 병렬 알고리즘은 상당한 계산량을 요구하는 수중정합처리 알고리즘을 적절히 다중 프로세서에 균형 있게 분산시켜 프로세서의 개수와 비례하는 성능향상을 보여주고 있다.

• Journal of information and communication convergence engineering
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• 제11권4호
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• pp.298-306
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• 2013

The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 학술대회 논문집 전문대학교육위원
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• 제어로봇시스템학회논문지
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• 제19권12호
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• pp.1072-1080
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• 2013

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

• 한국컴퓨터정보학회논문지
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• 제10권3호
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• pp.183-188
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• 2005

블록암호알고리즘의 기본 구조인 Feistel 구조는 순차처리 구조이므로 병렬처리가 곤란하다. 그러므로 본 논문은 이러한 순차처리 구조를 변형하여 Feistel 구조가 병렬처리가 가능하도록 하였다. 이를 이용하여 본 논문은 병렬 Feistel 구조를 가지는 DES를 설계하였다. 제안된 병렬 Feistel 구조는 자체의 구조적 문제 때문에 pipeline 방식을 사용할 수 없어 데이터 처리속도와 데이터 보안사이에서 trade-off관계를 가질 수밖에 없었던 DES등과 같은 블록암호알고리즘의 성능을 크게 향상 시킬 수 있었다. 그러므로 Feistel 구조를 적용한 SEED, AES의 Rijndael, Twofish 등에 제안된 방식을 적용할 경우 지금보다 더욱 우월한 보안 기능 및 고속의 처리능력을 발휘하게 될 것이다.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권7호
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• pp.465-472
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• 2004

Analog CPPN-based optimal road boundary detection algorithm for autonomous vehicle is proposed. The CPPN is a massively connected analog parallel array processor. In the paper, the dynamic programming which is an efficient algorithm to find the optimal path is implemented with the CPPN algorithm. If the image of road-boundary information is utilized as an inter-cell distance, and goals and start lines are positioned at the top and the bottom of the image, respectively, the optimal path finding algorithm can be exploited for optimal road boundary detection. By virtue of the parallel and analog processing of the CPPN and the optimal solution of the dynamic programming, the proposed road boundary detection algorithm is expected to have very high speed and robust processing if it is implemented into circuits. The proposed road boundary algorithm is described and simulation results are reported.

• 전기전자학회논문지
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• 제18권3호
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• pp.398-402
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• 2014

본 논문은 ROI-CENTRIST 기반 보행자 인식 알고리즘의 병렬처리 방식을 제안한다. 기존의 보행자 인식 방식만을 이용하여 임베디드 환경에서 보행자 인식을 실시간으로 처리하기에는 어려움이 존재한다. 이러한 문제는 기존의 알고리즘에 ROI를 적용한 방식을 병렬로 처리함으로써 해결할 수 있다. 본 논문에서 제안하는 ROI-CENTRIST 기반 보행자 인식의 병렬처리 방식은 기존의 CENTRIST 기반 보행자 인식 방식보다 약 10% 향상된 5.2 fps의 성능을 보인다.

• 제어로봇시스템학회논문지
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• 제5권4호
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• pp.403-410
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• 1999

In this study, a parallel algorithm has been developed that can quickly solve the optiaml control problem of large-scale dynamic systems. The algorithm adopts the sequential quadratic programming methods and achieves domain decomposition-type parallelism in computing sensitivities for search direction computation. A silicon wafer thermal process problem has been solved using the algorithm, and a parallel efficiency of 45% has been achieved with 16 processors. Practical methods have also been investigated in this study as a way to further speed up the computation time.

• 전기학회논문지
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• 제56권10호
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• pp.1699-1708
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• 2007

The optimal power flow(OPF) problem was introduced by Carpentier in 1962 as a network constrained economic dispatch problem. Since then, the OPF problem has been intensively studied and widely used in power system operation and planning. In these days, OPF is becoming more and more important in the deregulation environment of power pool and there is an urgent need of faster solution technique for on-line application. To solve OPF problem, many heuristic optimization methods have been developed, such as Genetic Algorithm(GA), Evolutionary Programming(EP), Evolution Strategies(ES), and Particle Swarm Optimization(PSO). Especially, PSO algorithm is a newly proposed population based heuristic optimization algorithm which was inspired by the social behaviors of animals. However, population based heuristic optimization methods require higher computing time to find optimal point. This shortcoming is overcome by a straightforward parallel processing of PSO algorithm. The developed parallel PSO algorithm is implemented on a PC cluster system with 6 Intel Pentium IV 2GHz processors. The proposed approach has been tested on the IEEE 30-bus system. The results showed that computing time of parallelized PSO algorithm can be reduced by parallel processing without losing the quality of solution.