• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.183-188
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• 2002

The forecast of a container traffic has been very important for port and development. Generally, Statistic methods, such as moving average method, exponential smoothing, and regression analysis have been much used for traffic forecasting. But, considering various factors related to the port affect the forecasting of container volume, neural network of parallel processing system can be effective to forecast container volume based on various factors. This study discusses the forecasting of volume by using the neural, network with back propagation learning algorithm. Affected factors are selected based on impact vector on neural network, and these selected factors are used to forecast container volume. The proposed the forecasting algorithm using neural network was compared to the statistic methods.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.345-352
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• 2006

The purpose of this paper is to evaluate the efficiency of two yard layout of HSS at container terminal, one is that the container yard blocks are placed horizontally in parallel with berth, the other is that the yard blocks are arranged vertically in perpendicular to the berth. In stevedoring system of container terminal, stacking and transport performance are influenced according to block arrangement type of yard. Therefore, efficient design that can improve stacking and transport performance is required. In this paper, we compared their efficiency of two block arrangement concepts in terms of storage capacity, productivity, facility investments, truck service level.

• Journal of the Korean Society of Mechanical Technology
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• v.13 no.2
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• pp.79-84
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• 2011

In general, a valve body of the automatic transmission(AT) is controlled by the clutch, the brake and lubricating oil flow in a hydraulic system and lubricant flow for each valve can be adjusted independently. To increase the lifetime of AT, the lubrication flow rate in a valve body for a 6 speed AT based parallel hybrid electric vehicle must be provided with proper oil distribution and control. In this study, we carried out several experiments without the inner parts of AT and with a AT assembly. The variation of the flow rate on oil temperature and pressure between an oil supply port and the outlets of the lubrication port was evaluated and analyzed. In the case of AT without the inner parts, it was evident that as the oil required for an operation of the clutch and brake was discharged from the outlet port, the flow rate from each lubrication port is decreased. However, the flow rate of the AT assembly was slightly increased. In addition, the lubrication flow rate was increased with increasing the oil temperature, and also it was reduced with increasing the oil pressure. Details of the resulting data are discussed.

• Journal of Navigation and Port Research
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• v.28 no.10 s.96
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• pp.875-879
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• 2004

In this paper, sub-harmonic pumped(SHP) mixer using anti-parallel diode pair(APDP) is designed for 5 GHz band wireless communication system. Conventional mixers mix LO with RF, and obtain IF signal from the difference between LO and RF. As the frequency increase, LO signal requires higher LO power, better phase noise characteristics, more stable La. However, using APDP, the SHP mixer mixes the 2nd harmonics of LO signal. Therefore, the SHP mixer has an advantage that the LO signal frequency required for IF signal is reduced at half value of LO fundamental frequency. When LO power is 3 dBm, the conversion loss of manufactured SHP mixer is 12.83 dB. The isolation of LO/IF, 2LO/IF, RF/1F and LO/RF is 39.17 dB, 58 dB, 34 dB, and 67.9 dB. respectively. For this case, IP3 at input is 8 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Journal of Advanced Navigation Technology
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• v.23 no.4
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• pp.309-315
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• 2019

This paper proposes an implementation of unequal power divider with 1:3 and 1:4 splitting ratio in multi-section structure using CPW and offset coupled transmission line. The power divider consists of a multi-section transmission line and a circuit with parallel capacitors and resistors. A multi-section transmission line was implemented by decomposing a ${\lambda}/4$ single transmission line terminated by an arbitrary impedance and converging it with a multi-section transmission line shorter than $90^{\circ}$ electrical length, and RC parallel circuits were connected between transmission lines to obtain reflection coefficient of output port and isolation characteristics between the output port. In this way, it was confirmed that the transmission lines at the unequal power divider designed at 2 GHz were shorter than ${\lambda}/4$ and implemented at least 27% less than the conventional ones, and that the broadband characteristics could be obtained.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.485-490
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• 2017

In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 1994.10a
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• pp.79-90
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• 1994

The goal of this research is to get a measuring system for absorption characteristics of electromagnetic wave absorbers in ferrite type which are lat grid-type special type etc. It is however very difficult to measure the absorption characteristics as in low frequency as in 30 MHz, To solve the problem therefore we propose a standing wave method and a measurement method in time domain using parallel striplines construct the measuring system and measure the characteristics of ferrite microwave absorbers in grid type using the proposed measuring system.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.1-7
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• 1997

In ahigh power amplifier design, power combiner/divider is used to connect low power amplifiers in parallel. The raidal structure of the powe combiner/divider has not only a good characteristics of port-to-port isolation but also an advantage of giving a redundancy to the structure itself by using RF switches. The parastics of a power resistor, that would be a problem in design process, are removed by both slot lines and cavity resonators, and the comon node in the circuit is rdesigned as a planar topology, and thus a new type of 4-way radial power combiner/divider is accomplished at 1840 ~ 1870 MH PCS frequency band. The insertion loss, reflection, and isolation characteristics of 40way radial power combiner/divider which can be adaptable to PCS system in this thesis are -0.3dB, -24dB,a dn -27dB respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.3
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• pp.3-7
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• 2010

As the distance between signal lines in memories of high density ICs like SoCs decreases rapidly, failure occurs more frequently and effective memory test techniques are needed. In this paper, a new SRAM structure is proposed to decrease test complexity and test time for embedded DRAMs. In the presented technique, because memory test can be handled as a single port testing and read-write operation is possible at dual port without high complexity, test time can be much reduced.