• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.10
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• pp.50-62
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• 1996

A parallel looking stereo camera was mainly used as an input sensor for digital image processing, image understanding and the extraction of 3 dimensional information. Theoretical analysis and performance evaluation are dealt in this paper for a convergent looking stereo camera model having a fixation point with the result of crossing optical axes. The quantization error, depth resolution and equidepth map due to digital pixels, and the misalignments effects of pan, tilt and roll angles are analyzed by using rhe relationship between the reference and image coordinate systems. Also horopter, epipolar lines, probability density functions of the depth error, and stereo fusion areas for the two camera models are discussed.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.475-482
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• 2023

Synthetic Aperture Radar (SAR), which provides images of targets using radio signals, enables monitoring at all times regardless of weather conditions. In this paper, the SAR system was installed on the test aircraft to collect SAR raw data on the ground and the sea, and the results of image formation using the backprojection algorithm were presented.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.10-15
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• 2015

This paper proposes the parallel implementation of a self-similarity based image SR (super-resolution) algorithm using OpenCL. The SR algorithm requires tremendous computations to search for a similar patch. This becomes a bottleneck for the real-time conversion from a FHD image to UHD. Therefore, it is imperative to accelerate the processing speed of SR algorithms. For parallelization, the SR process is divided into several kernels, and memory optimization is performed. In addition, two GPUs are used for further acceleration. The experimental results shows that a GPGPU implementation can speed up over 140 times compared to a single-core CPU. Furthermore, it was confirmed experimentally that utilizing two GPUs can speed up the execution time proportionally, up to 277 times.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.96-100
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• 1998

Due to expected wide spread use of DCT based image/video coding standard, it is advantageous to process data directly in the DCT domain rather than decoding the source back to the spatial domain. The block processing algorithm provides a parallel processing method since multiple input data are processed in the block filter structure. Hence a fast implementation of the algorithm is well suited. In this paper, we propose the JPEG browse by Block Transform Domain Filtering(BTDF) using subband filter banks. Instead of decompressing the entire image to retrieve at full resolution from compressed format, a user can select the level of expansion required$(2^N{\times}2^N)$. Also this approach reduces the computer cpu time by reducing the number of multiplication through BTDF in the filter banks.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.10
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• pp.1551-1560
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• 1997

This study is devoted to the detection of the 3-dimensional point obstacles on the plane by using accumulated scan line images. The proposed accumulating only one scan line allow to process image at real time. And the change of motion of the feature in image is small because of the short time between image frames, so it does not take much time to track features. To obtain recursive optimal obstacles position and robot motion along to the motion of camera, Kalman filter algorithm is used. After using Kalman filter in case of the fixed environment, 3-dimensional obstacles point map is obtained. The position and motion of moving obstacles can also be obtained by pre-segmentation. Finally, to solve the stereo ambiguity problem from multiple matches, the camera motion is actively used to discard mis-matched features. To get relative distance of obstacles from camera, parallel stereo camera setup is used. In order to evaluate the proposed algorithm, experiments are carried out by a small test vehicle.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.30-38
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• 1995

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.1135-1139
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• 1989

Three layered neural network was applied for the pattern recognition problem of human spermatozoa in clinical test. The goodness of recognition rate was studied in relation to the number of hidden layer cells and of output layer cells. The proposed method provided better results than conventional template matching technique. Parallel processing of the back propagation learning algorithm was also studied using transputers and its performance was evaluated.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.1
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• pp.39-52
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• 1996

본 논문에서는 고속 영상자료를 병렬 암호화 할 수 있는 새로운 알고리즘을 제안하였다. 암호화 테이블과 스케닝 순서, 스크램블 등의 문제점들을 개선하였다. 입력자료들은 독립된 블럭으로 분리되며 각 블럭들은 같은 암호화 알고리즘을 통하여 암호화 된다. 그러므로 시스템이 n개의 처리기로 구성되어 있으면, 전체 처리시간이 1/n로 감소됨이 기대된다. 또한 대표성이라는 개념을 적용한 결과, 높은 비도를 갖는 키를 사용한 효과르 얻을 수 있다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.