• Journal of Power Electronics
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• 제19권3호
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• pp.665-675
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• 2019

Renewable energy based on photovoltaic systems is beginning to play an important role to supply power to remote areas all over the world. Owing to the lower output voltage of photovoltaic arrays, high gain DC-DC converters with a high efficiency are required in practice. This paper presents a novel interleaved DC-DC boost converter with a high voltage gain, where the input terminal is interlaced in parallel and the output terminal is staggered in series (IPOSB). The IPOSB configuration can reduce input current ripples because two inductors are interlaced in parallel. The double output capacitors are charged in staggered parallel and discharged in series for the load. Therefore, IPOSB can attain a high step-up conversion and a lower output voltage ripple. In addtion, the output voltage can be automatically divided by two capacitors, without the need for extra sharing control methods. At the same time, the voltage stress of the power devices is lowered. The inrush current problem of capacitors is restrained by the inductor when compared with high gain converters with a switching-capacitor structure. The working principle and steady-state characteristics of the converter are analyzed in detail. The correctness of the theoretical analysis is verified by experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.433-437
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• 1998

Equalize SOC of the cell which effect on the charge.discharge ability and the efficiency of the battery, through the charge.discharge characteristic test of the battery source, and develope the high efficiency charge.discharge system in the series HEV have a constant engine-generator output. For this, in this paper, establish the electrical model and the condition of high efficiency charge.discharge, and proposed the improvement method of charge.discharge characteristic in the battery source that consist of twenty Ni-MH cells connected serial/parallel

• 정보처리학회논문지A
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• 제10A권2호
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• pp.111-122
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• 2003

군사용 워게임 시뮬레이션 모델들의 상호연동을 위해서는 국제표준연동(HLA : High Level Architecture)구조를 반드시 갖추어야하며 타 모델과 연동시 발생되는 시스템 오버헤드를 줄이기 위해서는 병렬 시뮬레이션 엔진 도입이 효과적이다. 그러나 기존 군사용 워게임 시뮬레이션 모델엔진의 이벤트 처리는 순차적 이벤트-드리븐 방식으로 처리하고 있다. 이는 병렬로 처리 시 글로벌 자료영역에 대한 동시참조등의 문제점들이 발생하기 때문이다. 아울러 기존 시뮬레이션 플랫폼으로 다중 CPU 시스템을 사용하여도 여러 개의 CPU를 다 활용하지 못하는 결과를 초래하고 있다. 따라서 이 논문에서는 군사용 워 게임 모델의 시스템 처리능력 향상과 글로벌 자료 영역에 대한 동시참조, 대외적인 시뮬레이션 시간처리, 장애 회복(Crash Recovery)시 병행 처리된 이벤트들의 순서를 보장 할 수 있는 객체모델에 기반한 병렬 시뮬레이션 엔진으로의 전환을 제안한다 이 전환된 병렬 시뮬레이션 엔진은 다중 CPU 시스템(SMP)상에서도 병렬 실행이 가능하도록 설계하고 구현하였다.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.307-312
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• 2002

For accuracy of an experiment, measure changing of grounding resistance by short period after construction and investigated the efficiency of grounding's different methode of parallel connection. We could confirm on measurement's accuracy, error through comparing the theoretical value and measured value. Therefore, reduction ratio can be expected from execution measurement to receive a target resistance value. By the result, we could evaluate the method of rod grounding electrode's proper execution

• Journal of Power Electronics
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• 제13권2호
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• pp.322-328
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• 2013

This paper presents a modified Current Source Parallel Resonant Push-pull Inverter (CSPRPI) for single phase induction heating applications. One of the most important problems associated with current source parallel resonant inverters is achieving ZVS in transient intervals. This paper shows that a CSPRPI with the integral cycle control method has dynamic ZVS. According to this method, it is the Phase Locked Loop (PLL) circuit that tracks the switching frequency. The advantages of this technique are a higher efficiency, a smaller package size and a low EMI in comparison with similar topologies. Additionally, the proposed modification results in a low THD of the ac-line current. It has been measured as less than %2. To show the validity of the proposed method, a laboratory prototype is implemented with an operating frequency of 80 kHz and an output power of 400 W. The experimental results confirm the validity of the proposed single phase induction heating system.

• International Journal of Fluid Machinery and Systems
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• 제6권3호
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• pp.113-120
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• 2013

While performing numerical simulations, it is general industrial practice to neglect the clearance gap between the impeller and the inlet duct. In the present work, the effect of clearance gap on the performance of an industrial sized centrifugal blower is simulated for two volutes of width ratios and various flow coefficients. The results show that the clearance has a positive effect at low mass flow rates. This is observed in the pressure rise (1.3%) as well as in efficiency (0.7%). At higher mass flow rates, it has a negative effect with a drop in efficiency of 1% and pressure drop of about 1.4%. The effect of clearance gap on volute with higher width ratio is smaller when compared with the volute with smaller width ratio.

• IEIE Transactions on Smart Processing and Computing
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• 제6권4호
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• 제18권1호
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• pp.17-26
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• 2014

This paper presents development of an improved domain decomposition method for large scale structural problem that aims to provide high computational efficiency. In the previous researches, we developed the domain decomposition algorithm based on augmented Lagrangian formulation and proved numerical efficiency under both serial and parallel computing environment. In this paper, new computational analysis by the proposed domain decomposition method is performed. For this purpose, reduction in computational time achieved by the proposed algorithm is compared with that obtained by the dual-primal FETI method under serial computing condition. It is found that the proposed methods significantly accelerate the computational speed for a linear structural problem.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권4호
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• pp.175-182
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• 2000

The back-light inverter used in the laptop computer is designed in this paper. It has been difficult for electromagnetic transformer to enhance the efficiency and compact profile of the inverter. In this paper, (1) the piezoelectric transformer (PT) is used for reducing the loss; (2) the volumes of core and winding coil are used in electromagnetic transformer, and (3) the half-bridge series parallel resonant circuit is used in the driver of the inverter. The modified PT for this paper and the equivalent circuit are supported by the simulation program. The result of the experiment shows more than 91% improvement in terms of the efficiency.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.350-352
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• 1996

A Hight Efficiency Quasi-Parallel Resonant DC-Link Inverter which shows highly improved PWM capability, low loss characteristic and low voltage stress is presented. A method to minimize freewheeling interval, which is able to largely decrease DC-link operation losses and to steadily guarantee soft switching in the wide operation region is proposed. Analysis and simple experiments were performed to verify validity of the proposed inverter topology.