• Journal of Satellite, Information and Communications
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• v.10 no.1
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• pp.1-5
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• 2015

With the help of fast growing multimedia technology and high preference for users of large screens, the newest video coding standard, HEVC (High Efficiency Video Coding) high-quality video compression), has been introduced. Therefore, the high definition image services which are four times more clear than conventional HD video, are getting popular. JPEG 2000 also has stated to support 4K and 8K UHD. As a result, it requires fast processing technology to read and write UHD images. This paper introduces a study on fast parallel processing technology for UHD images. For this purpose, first, JPEG 2000 is reviewed and a GPU based parallel implementation is proposed for a preprocessing of color conversion stage. The parallelled algorithm is implemented with OpenCL (Open Computing Language). The simulation results show that the proposed method shows 5 times performance improvements on processing speed for 4K UHD over the method using threads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.51-59
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• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.80-89
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• 2001

The development in the mobile computing systems have arisen new and previously unforeseen problems, such as problems in information management of mobile host, disconnection of mobile host and low bandwidths of wireless communications. Especially, location information management strategy of mobile host results in an increased overhead in mobile computing systems. Due to the mobility of the mobiles host, the changes in the mobile host's address depends on the mobile host's location, and is maintained by mapping physical address on virtual address, Since previously suggested several strategies for mapping method between physical address and virtual address did not tackle the increase of mobile host and distribution of location information, it was not able to support the scalability in mobile computing systems. Thus, to distribute the location inrormation, we propose an advanced n-depth LiST (Location information Search Tree) and the parallel location search and update strategy based on the advanced n-depth LiST. The advanced n-depth LiST is logically a hierarchical structure that clusters the location information server by ring structure and reduces the location information search and update cost by parallel seatch and updated method. The experiment shows that even though the distance of two MHs that communicate with each other is large, due to the strnctural distribution of location information, advanced n-depth LiST results in good performance. Moreover, despite the reduction in the location information search cost, there was no increase in the location information update cost.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.7
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• pp.553-564
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• 1990

The co-efficient matrix of linear second-order partial differential equations in the general form is partitioned with (n-1)x(n-1) submartices and is transformed into the block tridiagonal system. Then the cyclic odd-even reduction technique is applied to this system with the large-grain data granularity and the block cyclic reduction algorithm to solve unknown vectors of this system is created. But this block cyclic reduction technique is not suitable for the parallel processing system because of its parallelism chanigng at every computing stages. So a new algorithm for solving linear second-order partical differential equations is presentes by the block cyclic reduction technique which is modified in order to keep its parallelism constant, and to reduce gteatly its execution time. Both of these algoriths are compared and studied.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.511-518
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• 2002

Symmetric Multiprocessors (SMP) has emerged as an important and cost-effective platform for high performance parallel computing. Scheduling of parallel tasks and communications of SMP is important because the choice of a scheduling discipline can have a significant impact on the performance of the system. In this paper, we present a task duplication based scheduling scheme for bus-based SMP. The proposed scheme pre-allocates network communication resources so as to avoid potential communication conflicts. The performance of the proposed scheme has been observed by comparing the schedule length under various number of processors and the communication cost.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.1-9
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• 2003

In GRID environments, an efficient load balancing algorithm should be adopted since the system performances of GRID system are not homogeneous. In this work, a new two-step mesh-partitioning scheme based on the graph-partitioning scheme was introduced to consider the difference of system performance. In the two-step mesh-partitioning scheme, the system performance weights were calculated to reflect the effect of heterogeneous system performances and WEVM(Weighted Edge and vertex Method) was adopted to minimize the increase' of communications. Numerical experiments were carried out in multi-cluster environment and WAN (Wide Area Network) environment to investigate the effectiveness of the two-step mesh-partitioning scheme.

• Journal of Communications and Networks
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• v.7 no.1
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• pp.13-20
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• 2005

In this paper, a new multi carrier, direct sequence code division multiple access (MC-DS-CDMA) system is proposed. Our new signal construction is based on convolutional encoding of the transmitted data, serial-to-parallel (S/P) conversion of the encoded data, Walsh-Hadamard-transformation (WHT), a second S/P conversion of the WHT outputs, spread spectrum (SS) modulation with a common pseudo-noise (PN) sequence, and then multicarrier transmission. The system bit error rate (BER) performance in frequency selective fading channel in the presence of additive white Gaussian noise (AWGN) and a jamming tone is analyzed and simulated. The numerical results are compared with those from an orthogonal MC-DS-CDMA system of Sourour and Nakagawa [7]. It is shown that the two systems have almost the same BER performance, but the proposed scheme has better anti-jamming ability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Bulletin of the Korean Chemical Society
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• v.31 no.12
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• pp.3639-3643
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• 2010

We have developed CUDA-enabled version of a general purpose molecular dynamics simulation code for GPU. Implementation details including parallelization scheme and performance optimization are described. Here we have focused on the non-bonded force calculation because it is most time consuming part in molecular dynamics simulation. Timing results using CUDA-enabled and CPU versions were obtained and compared for a biomolecular system containing 23558 atoms. CUDA-enabled versions were found to be faster than CPU version. This suggests that GPU could be a useful hardware for molecular dynamics simulation.