• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.523-525
• /
• 2008

Novel zero-voltage switching(ZVS) dual inductor-fed DC-DC converter integrating a conventional dual inductor-fed boost converter(DIFBC) and a parallel bidirectional boost converter has been proposed. Most of current-fed type boost topologies including dual inductor schemes have crucial defects such as a high voltage spike on the main switch when it comes to turning off, an unattainable soft start-up due to the limited range of duty ratio, above 50%, and considerable switching losses due to the hard switching. By adding two auxiliary switches and an output capacitor on the conventional DIFBC, the proposed circuit can solve mentioned problems and improve the efficiency with simple methods. The operational principle and theoretical analysis of the proposed converter have been included. Experimental results based on a 42V input, 400V/1A output and 50kHz prototype are shown to verify the proposed scheme.

• Journal of Power Electronics
• /
• v.9 no.3
• /
• pp.472-480
• /
• 2009

In this paper, a charge equalization converter with parallel-connected primary windings of transformers is proposed. The proposed work effectively balances the voltage among Lithium-Ion battery cells despite each battery cell has low voltage gap compared with its state of charge (SOC). The principle of the proposed work is that the equalizing energy from all battery strings moves to the lowest voltage battery through the isolated dc/dc converter controlled by the corresponding solid state relay switch. For this research a prototype of four Lithium-Ion battery cells is optimally designed and implemented, and experimental results show that the proposed method has excellent cell balancing performance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.1
• /
• pp.31-38
• /
• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.1193-1194
• /
• 2008

In this paper, we propose application training kit using parallel port circuit of standard architecture in computer system. The proposed training kit is verified through the design of hardware board and a virtual driving test using GUI method in VC++ under window XP operating system.

• Journal of Information Processing Systems
• /
• v.7 no.1
• /
• pp.63-74
• /
• 2011

As a powerful and flexible processor, the Graphic Processing Unit (GPU) can offer a great faculty in solving many high-performance computing applications. Sweep3D, which simulates a single group time-independent discrete ordinates (Sn) neutron transport deterministically on 3D Cartesian geometry space, represents the key part of a real ASCI application. The wavefront process for parallel computation in Sweep3D limits the concurrent threads on the GPU. In this paper, we present multi-dimensional optimization methods for Sweep3D, which can be efficiently implemented on the finegrained parallel architecture of the GPU. Our results show that the overall performance of Sweep3D on the CPU-GPU hybrid platform can be improved up to 4.38 times as compared to the CPU-based implementation.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2014.01a
• /
• pp.477-478
• /
• 2014

일반적으로 컴퓨터 클러스터는 제공하는 기능에 따라 구축 비용이 고가이며 공간 확보, 냉난방, 전원 등을 위한 유지 비용을 무시할 수 없다. 그러므로, 일반 개발자들이 컴퓨터 클러스터를 보유하는 것은 쉬운 일이 아니다. 이러한 상황에서 교육용 및 연구용으로 가격대비 성능이 만족스러운 라즈베리 파이를 기반으로 한 컴퓨터 클러스터를 구축하여 분산 컴퓨팅 및 클라우드 컴퓨팅 시스템 개발을 위한 테스트 베드로 활용하고자 한다. 본 논문의 실험 결과는 라즈베리 파이 클러스터가 병렬 프로그래밍을 위한 효과적인 테스트 베드가 될 수 있음을 보인다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.11a
• /
• pp.161-164
• /
• 2006

인터넷이 발전하면서 웹에는 같은 내용을 다양한 언어로 표현한 문서들이 많이 존재한다. 이와 같은 웹 문서의 성질을 이용하여, 이 논문은 웹으로부터 수집된 병렬문서(parallel document)를 이용하여 한영 병렬말뭉치 구축 시스템을 설계하고 구현한다. 이 논문에서 구축과정을 요약하면 다음과 같다. 첫째, 웹 문서수집기를 이용해서 웹으로부터 한영 웹문서(html 문서)를 각각 수집한다. 둘째, 수집된 각 언어의 웹 문서에서 불필요한 내용(태그와 광고 문구 등)을 제거하여 문장을 추출하고, 추출된 문장을 단락단위로 정렬한다. 셋째, 단락단위로 정렬된 문서를 문장정렬(sentence alignment) 방법을 이용해서 문장을 정렬한다. 끝으로 정렬된 병렬문장을 단어 단위로 분리하여 병렬말뭉치를 구축한다. 이와 같은 방법으로 이 논문에서는 약 42만 5천 문장의 한영 병렬말뭉치를 구축하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.250-253
• /
• 2011

Chip manufacture nowadays turned their attention from accelerating uniprocessors to integrating multiple cores on a chip. Moreover desktop graphic hardware is now starting to support general purpose computation. Desktop users are able to use multi-core CPU and GPU as a high performance computing resources these days. However exploiting parallel computing resources are still challenging because of lack of higher programming abstraction for parallel programming. The 2-dimensional discrete cosine transform (2D-DCT) algorithms are most computational intensive part of JPEG encoding. There are many fast 2D-DCT algorithms already studied. We implemented several algorithms and estimated its runtime on multi-core CPU and GPU environments. Experiments show that data parallelism can be fully exploited on CPU and GPU architecture. We expect parallelized DCT bring performance benefit towards its applications such as JPEG and MPEG.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2022.11a
• /
• pp.6-8
• /
• 2022

병렬처리시스템이 설계와 구축에서 가장 중요한 관점 중의 하나는 비용 대비 성능이다. 본 연구에서는 라즈베리파이 4를 클러스터 방식으로 연결하여 병렬처리 시스템을 구축하였을 때, 클러스터의 병렬처리 성능이 다른 병렬처리 시스템과 유사한 확장성과 병렬처리 성능을 보여주는지를 HPL 벤치마크를 통하여 검증하였다. 실험 결과 라즈베리파이 기반의 병렬처리 시스템이 클러스터의 크기에 따른 병렬 확장성이 있고, 다른 병렬처리 시스템들과 유사한 처리 성능을 가질 수 있음을 확인하였으며, 이를 통하여 라즈베리파이와 같은 저가의 처리장치로도 충분한 크기의 클러스터를 구성할 경우 높은 성능을 기대할 수 있음을 알 수 있다.

• Journal of applied mathematics & informatics
• /
• v.5 no.3
• /
• pp.571-584
• /
• 1998

We look for methods and conditions to make use of cyclicity in come matrix problems not only for parallel computa-tion but also to reduce the problem size and accelerate convergence. It has been shown that some form of reducibility not necessarily cyclicity is enough for such purposes.