• Journal of Broadcast Engineering
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• v.23 no.4
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• pp.526-535
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• 2018

Many steganography algorithms have been studied, and steganalysis for detecting stego images which steganography is applied to has also been studied in parallel. Especially, in the case of the image steganalysis, the features such as ALE, SPAM, and SRMQ are extracted from the statistical characteristics of the image, and stego images are classified by learning the classifier using various machine learning algorithms. However, these studies did not consider the effect of image size, aspect ratio, or message-embedding rate, and thus the features might not function normally for images with conditions different from those used in the their studies. In this paper, we analyze the classification rate of the SPAM-based image stegnalysis against variety image sizes aspect ratios and message-embedding rates and verify its versatility.

• Journal of Sensor Science and Technology
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• v.23 no.6
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• pp.368-376
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• 2014

In order to measure the segmental impedance of the body, a bioelectrical impedance measurement system (BIMS) using multi-frequency applying method and two-electrode method was implemented in this study. The BIMS was composed of constant current source, automatic gain control, and multi-frequency generation units. Three experiments were performed using the BIMS and a commercial impedance analyzer (CIA). First, in order to evaluate the performance of the BIMS, four RC circuits connected with a resistor and capacitor in serial and/or parallel were composed. Bioelectrical impedance (BI) was measured by applying multi-frequencies -5, 10, 50, 100, 150, 200, 300, 400, and 500 KHz - to each circuit. BI values measured by the BIMS were in good agreement with those obtained by the CIA for four RC circuits. Second, after measuring BI at each frequency by applying multi-frequency to the left and right forearm and the popliteal region of the body, BI values measured by the BIMS were compared to those acquired by the CIA. Third, when the distance between electrodes was changed to 1, 3, 5, 7, 9, 11, 13, and 15 cm, BI by the BIMS was also compared to BI from the CIA. In addition, BI of extracellular fluid (ECF) was measured at each frequency ranging from 10 to 500 KHz. BI of intracellular fluid (ICF) was calculated by subtracting BI of ECF measured at 500 kHZ from BI measured at seven frequencies ranging from 50 to 500 KHz. BI of ICF and ECF decreased as the frequency increased. BI of ICF sharply decreased at frequencies above 300 KHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.61.1-61.1
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• 2015

Nanoscale semiconductor plasma processing has become one of the most challenging issues due to the limits of physicochemical fabrication routes with its inherent complexity. The mission of future and emerging plasma processing for development of next generation semiconductor processing is to achieve the ideal nanostructures without abnormal profiles and damages, such as 3D NAND cell array with ultra-high aspect ratio, cylinder capacitors, shallow trench isolation, and 3D logic devices. In spite of significant contributions of research frontiers, these processes are still unveiled due to their inherent complexity of physicochemical behaviors, and gaps in academic research prevent their predictable simulation. To overcome these issues, a Korean plasma consortium began in 2009 with the principal aim to develop a realistic and ultrafast 3D topography simulator of semiconductor plasma processing coupled with zero-D bulk plasma models. In this work, aspects of this computational tool are introduced. The simulator was composed of a multiple 3D level-set based moving algorithm, zero-D bulk plasma module including pulsed plasma processing, a 3D ballistic transport module, and a surface reaction module. The main rate coefficients in bulk and surface reaction models were extracted by molecular simulations or fitting experimental data from several diagnostic tools in an inductively coupled fluorocarbon plasma system. Furthermore, it is well known that realistic ballistic transport is a simulation bottleneck due to the brute-force computation required. In this work, effective parallel computing using graphics processing units was applied to improve the computational performance drastically, so that computer-aided design of these processes is possible due to drastically reduced computational time. Finally, it is demonstrated that 3D feature profile simulations coupled with bulk plasma models can lead to better understanding of abnormal behaviors, such as necking, bowing, etch stops and twisting during high aspect ratio contact hole etch.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.7
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• pp.639-649
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• 2000

In the relational database systems, the join operation is one of the most time-consuming query operations. Many parallel join algorithms have been developed to reduce the execution time. Multiple hash join algorithm using allocation tree is one of most efficient ones. However, it may have some delay on the processing each node of allocation tree, which is occurred in tuple-probing phase by the difference between one page reading time of outer relation and the processing time of already read one. In this paper, to solve the performance degrading problem by the delay, we develop a join algorithm using the concept of 'synchronization of page execution time' for multiple hash joins. We reduce the processing time of each nodes in the allocation tree and improve the total system performance. In addition, we analyze the performance by building the analytical cost model and verify the validity of it by various performance comparison with previous method.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.4
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• pp.430-436
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• 2014

Matrix-star and Half-Pancake graphs are modified versions of Star graphs, and has some good characteristics such as node symmetry and fault tolerance. This paper analyzes embedding between Matrix-star and Half-Pancake graphs. As a result, Matrix-star graphs $MS_{2,n}$ can be embedded into Half-Pancake graphs $HP_{2n}$ with dilation 5 and expansion 1. Also, Half Pancake Graphs, $HP_{2n}$ can be embedded into Matrix Star Graphs, $MS_{2,n}$ with the expansion cost, O(n). This result shows that algorithms developed from Star Graphs can be applied at Half Pancake Graphs with additional constant cost because Star Graphs, $S_n$ is a part graph of Matrix Star Graphs, $MS_{2,n}$.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.7
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• pp.1234-1243
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• 1992

A systematic procedure to design fuzzy PID controllers is developed in this paper. The concept of local fuzzy control cell is proposed by introducing both an adequate global control rule and membership functions to simplify a fuzzy logic controller. Fuzzy decision is made by using algebraic product and parallel firing arithematic mean, and a defuzzification strategy is adopted for improving the computational efficiency based on nonfuzzy micro-processor. A direct method, transforming the typical output of quasi-linear fuzzy operator to the digital compensator of PID form, is also proposed. Finally, the proposed algorithm is applied to an DC-servo motor. It is found that this algorithm is systematic and robust through computer simulations and implementation of controller using Intel 8097 micro-processor.

• Communications for Statistical Applications and Methods
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• v.15 no.1
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• pp.125-136
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• 2008

In many practical engineering design problems, the form of objective functions is not given explicitly in terms of design variables. Given the value of design variables, under this circumstance, the value of objective functions is obtained by real/computational experiments such as structural analysis, fluid mechanic analysis, thermodynamic analysis, and so on. These experiments are, in general, considerably expensive. In order to make the number of these experiments as few as possible, optimization is performed in parallel with predicting the form of objective functions. Response Surface Methods (RSM) are well known along this approach. This paper suggests to apply Support Vector Machines (SVM) for predicting the objective functions. One of most important tasks in this approach is to allocate sample data moderately in order to make the number of experiments as small as possible. It will be shown that the information of support vector can be used effectively to this aim. The effectiveness of our suggested method will be shown through numerical example which is well known in design of engineering.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1485-1492
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• 1999

대규모 시스템 명세의 올바름을 검증하기 위한 유한 상태 LTS에 기반을 둔 CTL논리 적용에 있어 가장 큰 문제점은, 시스템 내부의 병렬 프로세스간의 상호작용으로 인한 상태폭발이다. 그러나 Modal mu-calculus 논리를 시스템 안전성 및 필연성 특성 명세에 사용하면, 행위에 의한 순환적 정의가 가능하므로 상태폭발 문제가 해결 가능하다. 본 논문에서는 LTS로 명세화된 통신 프로토콜 시스템 모델의 안전성 및 필연성 특성을 모형 검사 기법에 의해 검증함에 있어, 시제 논리로 사용된 Modal mu-calculus 안전성 및 필연성 논리식과 CTL 의 안전성 및 필연성 논리식의 극한값이 동일함을 두 논리식을 만족하는 상태 집합이 같다는 것을 보임으로써 증명한다. 증명된 결과는 I/O FSM 모델로 표현된 통신 프로토콜의 안전성 및 필연성 검사를 위해 이론적인 기반으로서, 컴퓨터를 이용한 모형검사 기법에 효과적인 방법으로 응용이 가능하다.Abstract In applying CTL-based model checking approach to correctness verification of large state transition system specifications, the major obstacle is the combinational explosion of the state space arising due to interaction of many loosely coupled parallel processes. If, however, the modal mu-calculus viewed as a CTL-based logic with recursion, is used to specify the safety and liveness property of a given system, it is possible to resolve this problem. In this paper, we discuss the problem of verifying communication protocol system specified in LTS, and prove that a logic expression specifying safety and liveness in modal mu-calculus is semantically identical to the maximum value of the expression in CTL. This relation is verified by the proof that the sets of states satisfying the two logic expressions are equivalent. The proof can be used as a theoretical basis for verifying safety and liveness of communication protocols represented as I/O FSM model.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.194-204
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• 2003

The performance of a shared memory multiprocessor system is dependent on the system software such as scheduling policy as well as hardware system. Most of existing simulators, however, do not support simulation for multi-programmed environment because they can execute only a single benchmark application at a time. We propose a multi-programmed simulation method on a program-driven simulator, which enables the concurrent executions of multiple parallel workloads contending for limited system resources. Using the proposed method, system developers can measure and analyze detailed effects of resource conflicts among the concurrent applications as well as the effects of scheduling policies on a program-driven simulator. As a result, the proposed multi-programmed simulation provides more accurate and realistic performance projection to design a multiprocessor system.