• Title/Summary/Keyword: Parallel Communication

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Performance Analysis of the Multi-User Detector Employing a Hybrid Interference Cancellation Scheme in a WCDMA System (WCDMA 시스템에서 Hybrid Interference Cancellation 기법을 적용한 다중사용자 검파기의 성능분석)

  • 서정욱;오창헌;장은영;조성준
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.2
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    • pp.221-227
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    • 2002
  • In this paper, in order to know the effect of the interference, we have analyzed the BER (Bit Error Rate) performance of the MUD(Multi-User Detector) employing HIC(Hybrid Interference Cancellation) scheme for the asynchronous WCDMA system based on 3GPP(3rd Generation Partnership Project) Spec. through the In this paper, in order to know the effect of the interference, we have analyzed the BER (Bit Error Rate) performance of the MUD(Multi-User Detector) employing HIC(Hybrid Interference Cancellation) scheme for the asynchronous WCDMA system based on 3GPP(3rd Generation Partnership Project) Spec. through the computer simulation. we have assumed Rayleigh fading channel. And we have compared its BER performance with SIC's(Successive Interference Cancellation) and with PIC's(Parallel Interference Cancellation), which are the representative schemes in the subtractive interference cancellation. From the results, it is shown that PlC or HIC is effective for high data-rate users and SIC of HIC for low data-rate users to eliminate the interference. Regardless of the data rate, it is reasonable to use the HIC structure for WCDMA system to satisfy all of users' services. The reason is that the SIC scheme in front of HIC can guarantee the performance of low power users to cancel the serious interference caused by the high power users, while PIC in the rear of it can guarantee the performance of high power users to cancel the interference caused by the low power users.

Electrical Characteristics of Copper Circuit using Inkjet Printing (잉크젯 프린팅 방식으로 형성된 구리 배선의 전기적 특성 평가)

  • Kim, Kwang-Seok;Koo, Ja-Myeong;Joung, Jae-Woo;Kim, Byung-Sung;Jung, Seung-Boo
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.3
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    • pp.43-49
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    • 2010
  • Direct printing technology is an attractive metallization method, which has become immerging as "Green technology" to the conventional photolithography, on account of low cost, simple process and environment-friendliness. In order to commercialize the printed electronics in industry, it is essential to evaluate the electrical properties of conductive circuits using direct printing technology. In this contribution, we focused on the electrical characteristics of inkjet-printed circuits. A Cu nanoink was inkjet-printed onto a Bisaleimide triazine(BT) substrate with parallel transmission line(PTL) and coplanar waveguide(CPW) type, then was sintered at $250^{\circ}C$ for 30 min. We calculated the resistivity of printed circuits through direct current resistance by the measurement of I-V curve: the resistivity was approximately 0.558 ${\mu}{\Omega}{\cdot}cm$ which is about 3.3 times that of bulk Cu. Cascade's probe system in the frequency range from 0 to 30 GHz were employed to measure the Scattering parameter(S-parameter) with or without a gap between the substrate and the probe station chuck. The result of measured S-parameter showed that all printed circuits had over 5 dB of return loss in the entire frequency range. In the curve of insertion loss, $S_{21}$, showed that the PTL type circuits had better transmission of radio frequency (RF) than CPW type.

Performance Analysis of Noncoherent OOK UWB Transceiver for LR-WPAN (저속 WPAN용 비동기 OOK 방식 UWB 송수신기 성능 분석)

  • Ki Myoungoh;Choi Sungsoo;Oh Hui-Myoung;Kim Kwan-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.11A
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    • pp.1027-1034
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    • 2005
  • IEEE802.15.4a, which is started to realize the PHY layer including high precision ranging/positioning and low data rate communication functions, requires a simple and low power consumable transceiver architecture. To satisfy this requirements, the simple noncoherent on-off keying (OOK) UWB transceiver with the parallel energy window banks (PEWB) giving high precision signal processing interface is proposed. The flexibility of the proposed system in multipath fading channel environments is acquired with the pulse and bit repetition method. To analyze the bit error rate (BER) performance of this proposed system, a noise model in receiver is derived with commonly used random variable distribution, chi-square. BER of $10^{-5}$ under the line-of-sight (LOS) residential channel is achieved with the integration time of 32 ns and signal to noise ratio (SNR) of 15.3 dB. For the non-line-of-sight (NLOS) outdoor channel, the integration time of 72 ns and SNR of 16.2 dB are needed. The integrated energy to total received energy (IRR) for the best BER performance is about $86\%$.

A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization (GPGPU 자원 활용 개선을 위한 블록 지연시간 기반 워프 스케줄링 기법)

  • Thuan, Do Cong;Choi, Yong;Kim, Jong Myon;Kim, Cheol Hong
    • KIPS Transactions on Computer and Communication Systems
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    • v.6 no.5
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    • pp.219-230
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    • 2017
  • General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

The Play of Korean Preschool Children (취학전 아동의 놀이 형태 분석)

  • Choi, Jeen
    • Korean Journal of Child Studies
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    • v.1
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    • pp.15-27
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    • 1980
  • PURPOSE This study was intended to analyze the play-form of normal preschool children as related to age, sex, educational experience and social maturity. METHOD 1. Subjects The subjects of this study were eighty seven 3-, 4- and 5-year-old preschool children attending educational institutions in Seoul. 2. Instruments The instruments used in this study consisted of twenty one-minute observations in 5 preschool settings and a questionnaire designed to measure the children's social maturity filled in by their parents. The observations provided information on the children's free play, that is 1) play-form: solitary, parallel and group play 2) use/non-use of toys 3) behavior: play, activity, doing nothing, onlooking 4) stationary/moving dimensions 5) play group size The questionnaire measured such factors as communication, socialization, locomotion, self-help and self-direction. 3. Data Analysis Data analysis consisted of percentage and Chi square. RESULTS 1. Play-Form The relationship between age and play-form proved to be significant at the .05 level. That is, in both boys and girls, solitary play decreased with age and group play increased with age while parallel play maintained a similar position. The relationship between sex and play-form proved to be significant at the .05 level in 3-& 4-year-old children, but not significant in 5-year-old children. That is, in their $3^{rd}$ year boys engage in the solitary play more than girls and in their $4^{th}$ year boys engage in more group play than girls. 2. Toys Without differentiation of sex and age, cases of using toys in play exceed those cases where toys were not used. 3. Behavior The relationship between age and behavior proved to be significant at the .05 level in both boys and girls. That is, with increase of age, play decreased and activity increased in boys while play increased and doing nothing decreased in girls. 4. Moving Status Totally, moving occurred more frequently in play than stationary status. Moving proved not to have a significant relationship with age, but it did Navel a significant relationship with sex at the .05 level. That is, moving tended to increase with the increase in age in both boys and girls, but not at a significant level. Boys moved significantly more than girls in all three age levels. 5. The Relationship between Educational Experience and Play-Form There was a tendency for children with longer preschool experience to engage in less solitary play and more group play than children who had less than one semester of preschool experience, but this difference was not statistically significant. 6. The Relationship between Social Maturity and Play-Form The high social maturity group engaged in less solitary play and more group play than the low social maturity group, but this was not a statistically significant difference. 7. Play Group Size Play group size was 2~10 children, but the majority of play groups consisted of 2~3 children. There was a tendency for play groups composed of 2 children to decrease with age and play groups composed of 3 children to increase with age. No significant difference was found between the sexes in play group size.

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Flow Effects on Tailored RF Gradient Echo (TRFGE) Magnetic Resonance Imaging : In-flow and In-Plane Flow Effect (Tailored RF 경자사계방향 (TRFGE} 자기공명영상(MRI)에서 유체에 의한 영상신호 변화 : 유체유입효과와 영상면내를 흐르는 유체의 효과에 대하여)

  • Mun, Chi-Ung;Kim, Sang-Tae;No, Yong-Man;Im, Tae-Hwan;Jo, Jang-Hui
    • Journal of Biomedical Engineering Research
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    • v.18 no.3
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    • pp.243-251
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    • 1997
  • In this paper, we have reported two interesting flow effects arising in the TRFGE sequence using water flow phantom. First, we have shown that the TRFGE sequence is indeed not affected by "in-flow" effect from the unsaturated spins flowing into the imaging slice. Second, the enhancement of "in-plane flow" signal in the readout gradient direction was observed when the TRFGE sequence was used without flow compensation. These two results have many interesting applications in MR imaging other than fMRI. Results obtained were also compared with the results obtained by the conventional gradient echo(CGE) imaging. Experiments were performed at 4.7T MRI/S animal system (Biospec, BRUKER, Switzerland). A cylindrical phantom was made using acryl and a vinyl tube was inserted at the center(Fig. 1). The whole cylinder was filled with water doped with $MnCl_2$ and the center tube was filled with saline which flows in parallel to the main magnetic field along the tube. Tailored RF pulse was designed to have quadratic ($z^2$) phase distribution in slice direction(z). Imaging parameters were TR/TE = 55~85/10msec, flip angle = $30^{\circ}$, slice thickness = 2mm, matrix size = 256${\times}$256, and FOV= 10cm. In-flow effect : Axial images were obtained with and without flow using the CGE and TRFGE sequences, respectively. The flow direction was perpendicular to the image slice. In-plane flow : Sagittal images were obtained with and without flow using the TRGE sequence. The readout gradient was applied in parallel to the flow direction. We have observed that the "in-flow" effect did not affect the TRFGE image, while "in-plane flow" running along the readout gradient direction enhanced the signal in the TRFGE sequence when flow compensation gradient scheme was not used.

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Efficient Collaboration Method Between CPU and GPU for Generating All Possible Cases in Combination (조합에서 모든 경우의 수를 만들기 위한 CPU와 GPU의 효율적 협업 방법)

  • Son, Ki-Bong;Son, Min-Young;Kim, Young-Hak
    • KIPS Transactions on Computer and Communication Systems
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    • v.7 no.9
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    • pp.219-226
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    • 2018
  • One of the systematic ways to generate the number of all cases is a combination to construct a combination tree, and its time complexity is O($2^n$). A combination tree is used for various purposes such as the graph homogeneity problem, the initial model for calculating frequent item sets, and so on. However, algorithms that must search the number of all cases of a combination are difficult to use realistically due to high time complexity. Nevertheless, as the amount of data becomes large and various studies are being carried out to utilize the data, the number of cases of searching all cases is increasing. Recently, as the GPU environment becomes popular and can be easily accessed, various attempts have been made to reduce time by parallelizing algorithms having high time complexity in a serial environment. Because the method of generating the number of all cases in combination is sequential and the size of sub-task is biased, it is not suitable for parallel implementation. The efficiency of parallel algorithms can be maximized when all threads have tasks with similar size. In this paper, we propose a method to efficiently collaborate between CPU and GPU to parallelize the problem of finding the number of all cases. In order to evaluate the performance of the proposed algorithm, we analyze the time complexity in the theoretical aspect, and compare the experimental time of the proposed algorithm with other algorithms in CPU and GPU environment. Experimental results show that the proposed CPU and GPU collaboration algorithm maintains a balance between the execution time of the CPU and GPU compared to the previous algorithms, and the execution time is improved remarkable as the number of elements increases.

Channel Searching Method of IEEE 802.15.4 Nodes for Avoiding WiFi Traffic Interference (WiFi 트래픽 간섭을 피하기 위한 IEEE 802.15.4 노드의 채널탐색방법)

  • Song, Myong Lyol
    • Journal of Internet Computing and Services
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    • v.15 no.2
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    • pp.19-31
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    • 2014
  • In this paper, a parallel backoff delay procedure on multiple IEEE 802.15.4 channels and a channel searching method considering the frequency spectrum of WiFi traffic are studied for IEEE 802.15.4 nodes to avoid the interference from WiFi traffic. In order to search the channels being occupied by WiFi traffic, we analyzed the methods measuring the powers of adjacent channels simultaneously, checking the duration of measured power levels greater than a threshold, and finding the same periodicity of sampled RSSI data as the beacon frame by signal processing. In an wireless channel overlapped with IEEE 802.11 network, the operation of CSMA-CA algorithm for IEEE 802.15.4 nodes is explained. A method to execute a parallel backoff procedure on multiples IEEE 802.15.4 channels by an IEEE 802.15.4 device is proposed with the description of its algorithm. When we analyze the data measured by the experimental system implemented with the proposed method, it is observed that medium access delay times increase at the same time in the associated IEEE 802.15.4 channels that are adjacent each other during the generation of WiFi traffic. A channel evaluation function to decide the interference from other traffic on an IEEE 802.15.4 channel is defined. A channel searching method considering the channel evaluations on the adjacent channels together is proposed in order to search the IEEE 802.15.4 channels interfered by WiFi, and the experimental results show that it correctly finds the channels interfered by WiFi traffic.

Study of an In-order SMT Architecture and Grouping Schemes

  • Moon, Byung-In;Kim, Moon-Gyung;Hong, In-Pyo;Kim, Ki-Chang;Lee, Yong-Surk
    • International Journal of Control, Automation, and Systems
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    • v.1 no.3
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    • pp.339-350
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    • 2003
  • In this paper, we propose a simultaneous multithreading (SMT) architecture that improves instruction throughput by exploiting instruction level parallelism (ILP) and thread level parallelism (TLP). The proposed architecture issues and completes instructions belonging to the same thread in exact program order. The issue and completion policy greatly reduces the design complexity and hardware cost of our architecture, compared with others that employ out-of-order issue and completion. On the other hand, when the instructions belong to different threads, the issue and completion orders for those instructions may not necessarily be identical to the fetch order. The processor issues instructions simultaneously from multiple threads to functional units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably improves performance and resource utilization with minimal additional hardware cost over the conventional superscalar processors. This paper proposes an SMT architecture with grouping as well as one without grouping. Without grouping, all threads dynamically and flexibly share most resources. On the other hand, in the SMT architecture with grouping, in which resources and threads are divided into several groups for design simplification, resources are shared only among threads belonging to the same group as those resources. Simulation results show that our processors with four and eight threads improve performance by three or more times over the conventional superscalar processor with comparable execution resources and policies, and that reasonable grouping reduces the design complexity of SMT processors with little negative effect on performance.

Design of a 2.4GHz CMOS Low Noise Amplifier (2.4GHz CMOS 저잡음 증폭기)

  • 최혁환;오현숙;김성우;임채성;권태하
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.1
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    • pp.106-113
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    • 2003
  • In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.