• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.14-15
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• 2006

Application of the parallel Build-up is increasing continuously. This report presents about the PCB Build-up technology since 2000. Among the parallel build-up technologies, PALAP application - after making the via, filling the via with electric conductive paste, then expose to make wiring pattern and put them by layer without any glue or middle - is actively developing, especially DENSO company.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(3)
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• pp.29-32
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• 2001

In this paper, we applied the high-performance PGAP(Parallel Genetic Algorithm Processor) to recognizing rotated pattern. In order to perform this research efficiently, we used Multi-PGAP system consisted of four PGAP. In addition, we used mental rotation based on the rotated pattern recognition mechanism of human to reduce the number of operation. Also, we experimented with distinguishing specific pattern from similar coin patterns and determine rotated angle between patterns. The result showed that the development of future artificial recognition system is feasible by employing high performance PGAPS.

• Journal of applied mathematics & informatics
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• 제15권1_2호
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• pp.53-75
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• 2004

First, we present two classes of sequential algorithms for minimum flow problem: decreasing path algorithms and preflow algorithms. Then we describe another approach of the minimum flow problem, that consists of applying any maximum flow algorithm in a modified network. In section 5 we present several parallel preflow algorithms that solve the minimum flow problem. Finally, we present an application of the minimum flow problem.

• 산업기술연구
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• 제27권B호
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• pp.153-160
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• 2007

In this paper, the exact analysis of the parallel coupled line with open stub is presented. This structure shows LPF characteristics with broad stopband and sharp skirt characteristics. We derived the exact Z-matrix expression of the structure. In order to show the validation of the expression we designed $3^{th}$ order Chebyshev LPF using the structure. The simulated data excellently agreed with the predicted values by the calculation using the derived expression.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.323-324
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• 2013

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.271-272
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• 2009

• 대한수학회논문집
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• 제14권2호
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• pp.385-392
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• 1999

We deal with a differential equation which is constructed from homogeneous function, and its geometrical meaning in a Finsler space. Moreover, were prove that a locally Minkowski space satisfying a differential equation F\ulcorner=0 is flat-parallel.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2006년도 PARALLEL CFD 2006
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• pp.357-359
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• 2006

• 대한전기학회논문지:시스템및제어부문D
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• 제54권12호
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• 한국멀티미디어학회논문지
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• 제22권2호
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• pp.231-241
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• 2019

Bulk-loading an R-tree can be a good approach to build an efficient one. However, it takes a lot of time to bulk-load an R-tree for huge amount of data. In this paper, we propose a parallel R-tree construction scheme based on a Hadoop framework. The proposed scheme divides the data set into a number of partitions for which local R-trees are built in parallel via Map-Reduce operations. Then the local R-trees are merged into an global R-tree that covers the whole data set. While generating the partitions, it considers the spatial distribution of the data into account so that each partition has nearly equal amounts of data. Therefore, the proposed scheme gives an efficient index structure while reducing the construction time. Experimental tests show that the proposed scheme builds an R-tree more efficiently than the existing approaches.